4000
Dual 3-input NOR gates and inverter.
+---+--+---+ ________
|1 +--+ 14| VCC /1Y=1A+1B+1C
|2 13| 3C
1A |3 12| 3B __
1B |4 4000 11| 3A /2Y=2A
1C |5 10| /3Y
/1Y |6 9| /2Y ________
GND |7 8| 2A /3Y=3A+3B+3C
+----------+
4001
Quad 2-input NOR gates.
+---+--+---+ +---+---*---+ ___
1A |1 +--+ 14| VCC | A | B |/Y | /Y = A+B
1B |2 13| 4B +===+===*===+
/1Y |3 12| 4A | 0 | 0 | 1 |
/2Y |4 4001 11| /4Y | 0 | 1 | 0 |
2A |5 10| /3Y | 1 | 0 | 0 |
2B |6 9| 3B | 1 | 1 | 0 |
GND |7 8| 3A +---+---*---+
+----------+
4002
Dual 4-input NOR gates.
+---+--+---+ +---+---+---+---*---+ _________
/1Y |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = (A+B+C+D)
1A |2 13| /2Y +===+===+===+===*===+
1B |3 12| 2D | 0 | 0 | 0 | 0 | 1 |
1C |4 4002 11| 2C | 0 | 0 | 0 | 1 | 0 |
1D |5 10| 2B | 0 | 0 | 1 | X | 0 |
|6 9| 2A | 0 | 1 | X | X | 0 |
GND |7 8| | 1 | X | X | X | 0 |
+----------+ +---+---+---+---*---+
4006
Dual 4-bit and dual 5-bit serial-in serial-out shift registers with common clock.
+---+--+---+
1D |1 +--+ 14| VCC
/1Q4 |2 13| 1Q4
CLK |3 12| 2Q5
2D |4 4006 11| 2Q4
3D |5 10| 3Q4
4D |6 9| 4Q5
GND |7 8| 4Q4
+----------+
4007
Dual complementary CMOS pair and unbuffered inverter.
For use as simple inverters, connect 1pS=3pS=VCC, 1nS=3nS=GND, 1pD=1nD=/1Y and 2pD=2nD=/2Y.
+---+--+---+
1pD |1 +--+ 14| VCC
1pS |2 13| 2pD
1G |3 12| /3Y
1nS |4 4007 11| 3pS
1nD |5 10| 3G
2G |6 9| 3nS
GND |7 8| 2nD
+----------+
4008
4-bit binary full adder with fast carry.
+---+--+---+
A3 |1 +--+ 16| VCC S=A+B+CIN
B2 |2 15| B3
A2 |3 14| CO
B1 |4 13| S3
A1 |5 4008 12| S2
B0 |6 11| S1
A0 |7 10| S0
GND |8 9| CI
+----------+
4009
Hex inverters with level shifted outputs.
VDD may not be lower than VCC.
+---+--+---+ +---*---+ _
VCC |1 +--+ 16| VDD | A |/Y | /Y = A
/Y1 |2 15| /Y6 +===*===+
A1 |3 14| A6 | 0 | 1 |
/Y2 |4 13| | 1 | 0 |
A2 |5 4009 12| /Y5 +---*---+
/Y3 |6 11| A5
A3 |7 10| /Y4
GND |8 9| A4
+----------+
4010
Hex buffers with level shifted outputs.
VDD may not be lower than VCC.
+---+--+---+ +---*---+
VCC |1 +--+ 16| VDD | A | Y | Y = A
Y1 |2 15| Y6 +===*===+
A1 |3 14| A6 | 0 | 0 |
Y2 |4 13| | 1 | 1 |
A2 |5 4010 12| Y5 +---*---+
Y3 |6 11| A5
A3 |7 10| Y4
GND |8 9| A4
+----------+
4011
Quad 2-input NAND gates.
+---+--+---+ +---+---*---+ __
1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB
1B |2 13| 4B +===+===*===+
/1Y |3 12| 4A | 0 | 0 | 1 |
/2Y |4 4011 11| /4Y | 0 | 1 | 1 |
2A |5 10| /3Y | 1 | 0 | 1 |
2B |6 9| 3B | 1 | 1 | 0 |
GND |7 8| 3A +---+---*---+
+----------+
4012
Dual 4-input NAND gates.
+---+--+---+ +---+---+---+---*---+ ____
/1Y |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD
1A |2 13| /2Y +===+===+===+===*===+
1B |3 12| 2D | 0 | X | X | X | 1 |
1C |4 4012 11| 2C | 1 | 0 | X | X | 1 |
1D |5 10| 2B | 1 | 1 | 0 | X | 1 |
|6 9| 2A | 1 | 1 | 1 | 0 | 1 |
GND |7 8| | 1 | 1 | 1 | 1 | 0 |
+----------+ +---+---+---+---*---+
4013
Dual D flip-flop with set and reset.
+---+--+---+ +---+---+---+---*---+---+
1Q |1 +--+ 14| VCC | D |CLK|SET|RST| Q |/Q |
/1Q |2 13| 2Q +===+===+===+===*===+===+
1CLK |3 12| /2Q | X | X | 0 | 1 | 0 | 1 |
1RST |4 4013 11| 2CLK | X | X | 1 | 0 | 1 | 0 |
1D |5 10| 2RST | X | X | 1 | 1 | 1 | 1 |
1SET |6 9| 2D | 0 | / | 0 | 0 | 0 | 1 |
GND |7 8| 2SET | 1 | / | 0 | 0 | 1 | 1 |
+----------+ | X |!/ | 0 | 0 | - | - |
+---+---+---+---*---+---+
4014
8-bit parallel-in serial-out shift register with three parallel outputs.
+---+--+---+
P7 |1 +--+ 16| VCC
Q5 |2 15| P6
Q7 |3 14| P5
P3 |4 13| P4
P2 |5 4014 12| Q6
P1 |6 11| D
P0 |7 10| CLK
GND |8 9| LD//SH
+----------+
4015
Dual 4-bit serial-in parallel-out shift register with asynchronous reset.
+---+--+---+
2CLK |1 +--+ 16| VCC
2Q3 |2 15| 2D
1Q2 |3 14| 2RST
1Q1 |4 13| 2Q0
1Q0 |5 4015 12| 2Q1
1RST |6 11| 2Q2
1D |7 10| 1Q3
GND |8 9| 1CLK
+----------+
4016
Quad analog switches.
+---+--+---+
1X |1 +--+ 14| VCC
1Y |2 13| 1EN
2Y |3 12| 4EN
2X |4 4016 11| 4X
2EN |5 4066 10| 4Y
3EN |6 9| 3Y
GND |7 8| 3X
+----------+
4017
4-bit asynchronous decade counter with fully decoded outputs, reset and both active high and active low clocks.
The two CLK inputs are ANDed together, so that either can be used as clock or clock enable.
+---+--+---+
Q5 |1 +--+ 16| VCC
Q1 |2 15| RST
Q0 |3 14| CLK1
Q2 |4 13| /CLK2
Q6 |5 4017 12| RCO
Q7 |6 11| Q9
Q3 |7 10| Q4
GND |8 9| Q8
+----------+
4018
5-stage (divide by 2,4,6,8 or 10) Johnson counter with preset inputs.
+---+--+---+
D |1 +--+ 16| VCC
P1 |2 15| RST
P2 |3 14| CLK
/Q2 |4 13| /Q5
/Q1 |5 4018 12| P5
/Q3 |6 11| /Q4
P3 |7 10| PE
GND |8 9| P4
+----------+
4019
8-to-4 line noninverting data selector/multiplexer with OR function.
+---+--+---+ +---+---+---+---*---+
4A1 |1 +--+ 16| VCC | A0| A1| S1| S0| Y | Y=S0.A0+S1.A1
3A0 |2 15| 4A0 +===+===+===+===*===+
3A1 |3 14| S1 | X | X | 0 | 0 | 0 |
2A0 |4 13| Y4 | X | 0 | 0 | 1 | 0 |
2A1 |5 4019 12| Y3 | 0 | X | 1 | 0 | 0 |
1A0 |6 11| Y2 | X | 1 | X | 1 | 1 |
1A1 |7 10| Y1 | 1 | X | 1 | X | 1 |
GND |8 9| S0 +---+---+---+---*---+
+----------+
4020
14-bit asynchronous binary counter with reset.
Q1 and Q2 outputs missing.
+---+--+---+
Q11 |1 +--+ 16| VCC
Q12 |2 15| Q10
Q13 |3 14| Q9
Q5 |4 13| Q7
Q4 |5 4020 12| Q8
Q6 |6 11| RST
Q3 |7 10| /CLK
GND |8 9| Q0
+----------+
4021
8-bit parallel-in serial-out shift register with asynchronous load input and three parallel outputs.
+---+--+---+
P7 |1 +--+ 16| VCC
Q5 |2 15| P6
Q7 |3 14| P5
P3 |4 13| P4
P2 |5 4021 12| Q6
P1 |6 11| D
P0 |7 10| CLK
GND |8 9| LD//SH
+----------+
4022
3-bit asynchronous binary counter with fully decoded outputs, reset and both active high and active low clocks.
The two CLK inputs are ANDed together, so that either can be used as clock or clock enable.
+---+--+---+
Q1 |1 +--+ 16| VCC
Q0 |2 15| RST
Q2 |3 14| CLK1
Q5 |4 13| /CLK2
Q6 |5 4022 12| RCO
|6 11| Q4
Q3 |7 10| Q7
GND |8 9|
+----------+
4023
Triple 3-input NAND gates.
+---+--+---+ +---+---+---*---+ ___
1A |1 +--+ 14| VCC | A | B | C |/Y | /Y = ABC
1B |2 13| 3C +===+===+===*===+
2A |3 12| 3B | 0 | X | X | 1 |
2B |4 4023 11| 3A | 1 | 0 | X | 1 |
2C |5 10| /3Y | 1 | 1 | 0 | 1 |
/2Y |6 9| /1Y | 1 | 1 | 1 | 0 |
GND |7 8| 1C +---+---+---*---+
+----------+
4024
7-bit asynchronous binary counter with reset.
+---+--+---+
/CLK |1 +--+ 14| VCC
RST |2 13|
Q6 |3 12| Q0
Q5 |4 4024 11| Q1
Q4 |5 10|
Q3 |6 9| Q2
GND |7 8|
+----------+
4025
Triple 3-input NOR gates.
+---+--+---+ +---+---+---*---+ _____
1A |1 +--+ 14| VCC | A | B | C |/Y | /Y = A+B+C
1B |2 13| 3C +===+===+===*===+
2A |3 12| 3B | 0 | 0 | 0 | 1 |
2B |4 4025 11| 3A | 0 | 0 | 1 | 0 |
2C |5 10| /3Y | 0 | 1 | X | 0 |
/2Y |6 9| /1Y | 1 | X | X | 0 |
GND |7 8| 1C +---+---+---*---+
+----------+
4026
4-bit asynchronous decade counter with 7-segment decoder/common-cathode LED driver, display enable, ripple carry, reset and both active high and active low clocks.
+---+--+---+
CLK1 |1 +--+ 16| VCC
/CLK2 |2 15| RST
DEI |3 14| YC'
DEO |4 13| YC
CO |5 4026 12| YB
YF |6 11| YE
YG |7 10| YA
GND |8 9| YD
+----------+
4027
Dual J-K flip-flops with set and reset.
+---+--+---+ +---+---+---+---+---*---+---+
1Q |1 +--+ 16| VCC | J | K |CLK|SET|RST| Q |/Q |
/1Q |2 15| 2Q +===+===+===+===+===*===+===+
1CLK |3 14| /2Q | X | X | X | 1 | 1 | 1 | 1 |
1RST |4 13| 2CLK | X | X | X | 1 | 0 | 1 | 0 |
1K |5 4027 12| 2RST | X | X | X | 0 | 1 | 0 | 1 |
1J |6 11| 2K | 0 | 0 | / | 0 | 0 | - | - |
1SET |7 10| 2J | 0 | 1 | / | 0 | 0 | 0 | 1 |
GND |8 9| 2SET | 1 | 0 | / | 0 | 0 | 1 | 0 |
+----------+ | 1 | 1 | / | 0 | 0 |/Q | Q |
| X | X |!/ | 0 | 0 | - | - |
+---+---+---+---+---*---+---+
4028
1-of-10 noninverting decoder/demultiplexer.
+---+--+---+ +---+---+---+---*---+---+---+---+
Y4 |1 +--+ 16| VCC | S3| S2| S1| S0| Y0| Y1|...| Y9|
Y2 |2 15| Y3 +===+===+===+===*===+===+===+===+
Y0 |3 14| Y1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
Y7 |4 13| S1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
Y9 |5 4028 12| S2 | . | . | . | . | 0 | 0 | . | 0 |
Y5 |6 11| S3 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
Y6 |7 10| S0 | 1 | 0 | 1 | X | 0 | 0 | 0 | 0 |
GND |8 9| Y8 | 1 | 1 | X | X | 0 | 0 | 0 | 0 |
+----------+ +---+---+---+---*---+---+---+---+
4029
4-bit synchronous binary/decade up/down counter with preset and ripple carry output.
+---+--+---+
PE |1 +--+ 16| VCC
Q4 |2 15| CLK
P4 |3 14| Q3
P1 |4 13| P3
/RCI |5 4029 12| P2
Q1 |6 11| Q2
/RCO |7 10| U//D
GND |8 9| B//D
+----------+
4030
Quad 2-input XOR gates.
+---+--+---+ +---+---*---+ _ _
1A |1 +--+ 14| VCC | A | B | Y | Y = A$B = (A.B)+(A.B)
1B |2 13| 4B +===+===*===+
1Y |3 12| 4A | 0 | 0 | 0 |
2Y |4 4030 11| 4Y | 0 | 1 | 1 |
2A |5 10| 3Y | 1 | 0 | 1 |
2B |6 9| 3B | 1 | 1 | 0 |
GND |7 8| 3A +---+---*---+
+----------+
4031
64-bit serial-in serial-out shift register with multiplexed inputs.
Y is Q63 delayed by half a cycle (i.e. clocked on falling edge).
+---+--+---+
E |1 +--+ 16| VCC
CLK |2 15| D
|3 14|
|4 13|
Y |5 4031 12|
Q63 |6 11|
/Q63 |7 10| E//D
GND |8 9| CLKout
+----------+
4032
Triple serial adder.
Each section can be used to add long binary words, one bit on each clock cycle. CRST resets the internal carry flip-flop after one clock delay. The INV inputs can be used to invert the sum output (giving a 1’s-complemented result).
+---+--+---+
3S |1 +--+ 16| VCC
3INV |2 15| 3A
CLK |3 14| 3B
2S |4 13| 2A
2INV |5 4032 12| 2B
CRST |6 11| 1B
1INV |7 10| 1A
GND |8 9| 1S
+----------+
4033
4-bit asynchronous decade counter with 7-segment decoder/common-cathode LED driver, ripple blanking, ripple carry, reset and both active high and active low clocks.
+---+--+---+
CLK1 |1 +--+ 16| VCC
/CLK2 |2 15| RST
RBI |3 14| LT
RBO |4 13| YC
CO |5 4033 12| YB
YF |6 11| YE
YG |7 10| YA
GND |8 9| YD
+----------+
4034
8-bit bidirectional universal shift register with common serial input, dual parallel I/O ports and selectable synchronous/asynchronous parallel load.
+-----+--+-----+ +------+--------+-------+-------+
A7 |1 +--+ 24| VCC | B//A | LD//SH | A0..7 | B0..7 |
A6 |2 23| B7 +======+========+=======+=======+
A5 |3 22| B6 | 0 | 1 | in | out |
A4 |4 21| B5 | 1 | 1 | out | in |
A3 |5 20| B4 | 0 | 0 | Z | out |
A2 |6 19| B3 | 1 | 0 | out | Z |
A1 |7 4034 18| B2 +------+--------+-------+-------+
A0 |8 17| B1
ENA |9 16| B0
D |10 15| CLK
B//A |11 14| ASY//SY
GND |12 13| LD//SH
+--------------+
4035
4-bit inverting/noninverting universal shift register with J-/K inputs and asynchronous reset.
+---+--+---+
Q0 |1 +--+ 16| VCC
/INV |2 15| Q1
/K |3 14| Q2
J |4 13| Q3
RST |5 4035 12| P3
CLK |6 11| P2
LD//SH |7 10| P1
GND |8 9| P0
+----------+
4038
Triple negative-edge-triggered serial adder.
Each section can be used to add long binary words, one bit on each clock cycle. CRST resets the internal carry flip-flop after one clock delay. The INV inputs can be used to invert the sum output (giving a 1’s-complemented result).
+---+--+---+
3S |1 +--+ 16| VCC
3INV |2 15| 3A
/CLK |3 14| 3B
2S |4 13| 2A
2INV |5 4038 12| 2B
CRST |6 11| 1B
1INV |7 10| 1A
GND |8 9| 1S
+----------+
4040
12-bit asynchronous binary counter with reset.
+---+--+---+
Q11 |1 +--+ 16| VCC
Q5 |2 15| Q10
Q4 |3 14| Q9
Q6 |4 13| Q7
Q3 |5 4040 12| Q8
Q2 |6 11| RST
Q1 |7 10| /CLK
GND |8 9| Q0
+----------+
4041
Quad buffers with complementary outputs.
+---+--+---+ +---*---+---+
1Y |1 +--+ 14| VCC | A | Y |/Y | Y = A
/1Y |2 13| 4A +===*===+===+
1A |3 12| /4Y | 0 | 0 | 1 |
2Y |4 4041 11| 4Y | 1 | 1 | 0 |
/2Y |5 10| 3A +---*---+---+
2A |6 9| /3Y
GND |7 8| 3Y
+----------+
4042
4-bit transparent latch with selectable latch enable polarity and complementary outputs.
+---+--+---+ +---+---+---*---+---+
Q3 |1 +--+ 16| VCC | LE| LP| D | Q |/Q |
Q0 |2 15| /Q3 +===+===+===*===+===+
/Q0 |3 14| D3 | 0 | 0 | 0 | 0 | 1 |
D0 |4 13| D2 | 0 | 0 | 1 | 1 | 0 |
LE |5 4042 12| /Q2 | 1 | 0 | X | - | - |
LP |6 11| Q2 | 1 | 1 | 0 | 0 | 1 |
D2 |7 10| Q1 | 1 | 1 | 1 | 1 | 0 |
GND |8 9| /Q1 | 0 | 1 | X | - | - |
+----------+ +---+---+---*---+---+
4043
Quad 3-state S-R latches with overriding set.
+---+--+---+ +---+---+---*---+
1Q |1 +--+ 16| VCC | S | R | OE| Q |
2Q |2 15| 1R +===+===+===*===+
2R |3 14| 1S | X | X | 0 | Z |
2S |4 13| | 0 | 0 | 1 | - |
OE |5 4043 12| 4S | 0 | 1 | 1 | 1 |
3S |6 11| 4R | 1 | 0 | 1 | 0 |
3R |7 10| 4Q | 1 | 1 | 1 | 1 |
GND |8 9| 3Q +---+---+---*---+
+----------+
4044
Quad 3-state S-R latches with overriding reset.
+---+--+---+ +---+---+---*---+
1Q |1 +--+ 16| VCC | S | R | OE| Q |
|2 15| 4S +===+===+===*===+
2S |3 14| 4R | X | X | 0 | Z |
2R |4 13| 2Q | 0 | 0 | 1 | - |
OE |5 4044 12| 4R | 0 | 1 | 1 | 1 |
3S |6 11| 4S | 1 | 0 | 1 | 0 |
3R |7 10| 4Q | 1 | 1 | 1 | 0 |
GND |8 9| 3Q +---+---+---*---+
+----------+
4045
21-bit asynchronous binary counter with oscillator and reset input.
Only two 3% duty cycle outputs (180` out of phase) from the last counter stage are available. Can be used to generate a 1Hz clock signal using a 2.097152MHz crystal. P and N MOSFET source connections from the oscillator inverter are brought out of the package to allow the use of source resistors, but usually pS=VCC and nS=GND.
+---+--+---+
pS |1 +--+ 16| X1
nS |2 15| X0
VCC |3 14| GND
|4 13|
|5 4045 12|
|6 11|
QA |7 10|
QB |8 9|
+----------+
4046
Phase Locked Loop.
+---+--+---+
PCPout |1 +--+ 16| VCC
PC1out |2 15| Zener
PCinB |3 14| PCinA
VCOout |4 13| PC2out
/EN |5 4046 12| R2
C1A |6 11| R1
C1B |7 10| SFout
GND |8 9| VCOin
+----------+
4047
Low-power astable/monostable multivibrator with oscillator output.
+---+--+---+
Cext |1 +--+ 14| VCC
Rext |2 13| OSC
RCext |3 12| RETRIG
/AST |4 4047 11| /Q
AST |5 10| Q
/TR |6 9| RST
GND |7 8| TR
+----------+
4048
3-state 8-input multifunction gate.
+---+--+---+ +---+---+---+---*------------------------+
Y |1 +--+ 16| VCC | S2| S1| S0| OE| Output function |
OE |2 15| X +===+===+===+===*========================+
A |3 14| H | X | X | X | 0 | Z |
B |4 13| G | 0 | 0 | 0 | 1 | 8-input NOR |
C |5 4048 12| F | 0 | 0 | 1 | 1 | 8-input OR |
D |6 11| E | 0 | 1 | 0 | 1 | 2-wide 4-input OR-AND |
S1 |7 10| S2 | 0 | 1 | 1 | 1 | 2-wide 4-input OR-NAND |
GND |8 9| S0 | 1 | 0 | 0 | 1 | 8-input AND |
+----------+ | 1 | 0 | 1 | 1 | 8-input NAND |
| 1 | 1 | 0 | 1 | 2-wide 4-input AND-NOR |
| 1 | 1 | 1 | 1 | 2-wide 4-input AND-OR |
+---+---+---+---*------------------------+
4049
Hex inverters with high-to-low level shifter inputs.
+---+--+---+ +---*---+ _
VCC |1 +--+ 16| | A |/Y | /Y = A
/Y1 |2 15| /Y6 +===*===+
A1 |3 14| A6 | 0 | 1 |
/Y2 |4 13| | 1 | 0 |
A2 |5 4049 12| /Y5 +---*---+
/Y3 |6 11| A5
A3 |7 10| /Y4
GND |8 9| A4
+----------+
4066
Quad analog switches.
+---+--+---+
1X |1 +--+ 14| VCC
1Y |2 13| 1EN
2Y |3 12| 4EN
2X |4 4016 11| 4X
2EN |5 4066 10| 4Y
3EN |6 9| 3Y
GND |7 8| 3X
+----------+
4016
Quad analog switches.
+---+--+---+
1X |1 +--+ 14| VCC
1Y |2 13| 1EN
2Y |3 12| 4EN
2X |4 4016 11| 4X
2EN |5 4066 10| 4Y
3EN |6 9| 3Y
GND |7 8| 3X
+----------+
4050
Hex buffers with high-to-low level shifter inputs.
+---+--+---+ +---*---+
VCC |1 +--+ 16| | A | Y | Y = A
Y1 |2 15| Y6 +===*===+
A1 |3 14| A6 | 0 | 0 |
Y2 |4 13| | 1 | 1 |
A2 |5 4050 12| Y5 +---*---+
Y3 |6 11| A5
A3 |7 10| Y4
GND |8 9| A4
+----------+
4051
8-to-1 line analog multiplexer/demultiplexer with dual power supply.
VEE supply may not be more positive than GND.
+---+--+---+
X4 |1 +--+ 16| VCC
X6 |2 15| X2
Y |3 14| X1
X7 |4 13| X0
X5 |5 4051 12| X3
/EN |6 11| S0
VEE |7 10| S1
GND |8 9| S2
+----------+
4052
8-to-2 line analog multiplexer/demultiplexer with dual power supply.
VEE supply may not be more positive than GND.
+---+--+---+
1X0 |1 +--+ 16| VCC
1X2 |2 15| 2X2
1Y |3 14| 2X1
1X3 |4 13| 2Y
1X1 |5 4052 12| 2X0
/EN |6 11| 2X3
VEE |7 10| S0
GND |8 9| S1
+----------+
4053
Triple 2-to-1 line analog multiplexer/demultiplexer with dual power supply.
VEE supply may not be more positive than GND.
+---+--+---+
1X0 |1 +--+ 16| VCC
1X1 |2 15| 1Y
2X1 |3 14| 3Y
2Y |4 13| 3X1
2X0 |5 4053 12| 3X0
/EN |6 11| 3S
VEE |7 10| 1S
GND |8 9| 2S
+----------+
4054
Quad level shifters/LCD drivers with input latches.
A level-shifted inverse of the P (phase) input should be connected to the backplane of the LCD; this can be done by using one section of the 4054 with A=0 and LE=1.
+---+--+---+ +---+---*---+ _
1LE |1 +--+ 16| VCC | LE| A | R | Y = R$P
P |2 15| 1A +===+===*===+
1Y |3 14| 2LE | 0 | X | - |
2Y |4 13| 2A | 1 | 0 | 0 |
3Y |5 4054 12| 3LE | 1 | 1 | 1 |
4Y |6 11| 3A +---+---*---+
VEE |7 10| 4LE
GND |8 9| 4A
+----------+
4055
BCD to 7-segment decoder/LCD driver.
The Po (phase) output should be connected to the backplane of the LCD.
+---+--+---+
Po |1 +--+ 16| VCC
A2 |2 15| YF
A1 |3 14| YG
A3 |4 13| YE
A0 |5 4055 12| YD
Pi |6 11| YC
VEE |7 10| YB
GND |8 9| YA
+----------+
4056
BCD to 7-segment decoder/LCD driver with input latches.
A level-shifted inverse of the P (phase) input should be connected to the backplane of the LCD.
+---+--+---+
LE |1 +--+ 16| VCC
A2 |2 15| YF
A1 |3 14| YG
A3 |4 13| YE
A0 |5 4056 12| YD
P |6 11| YC
VEE |7 10| YB
GND |8 9| YA
+----------+
4059
Divide by N counter.
Ka, Kb, Kc are the modulus (divide by number) of the 1st and last counting sections. N can range from 3 to 15999. The down-counter is preset by 15 jam inputs.
+-----+--+-----+
CLK |1 +--+ 24| VCC
LD |2 23| Q
J1 |3 22| J5
J2 |4 21| J6
J3 |5 20| J7
J4 |6 19| J8
J16 |7 4059 18| J9
J15 |8 17| J10
J14 |9 16| J11
J13 |10 15| J12
Kc |11 14| Ka
GND |12 13| Kb
+--------------+
4060
14-bit asynchronous binary counter with oscillator and reset input.
Q0,Q1,Q2 and Q10 outputs are missing.
+---+--+---+
Q11 |1 +--+ 16| VCC
Q12 |2 15| Q9
Q13 |3 14| Q7
Q5 |4 13| Q8
Q4 |5 4060 12| RST
Q6 |6 11| X1
Q3 |7 10| X0
GND |8 9| X2
+----------+
4063
4-bit noninverting magnitude comparator with cascade inputs.
+---+--+---+
B3 |1 +--+ 16| VCC
IA<B |2 15| A3
IA=B |3 14| B2
IA>B |4 13| A2
OA>B |5 4063 12| A1
OA=B |6 11| B1
OA<B |7 10| A0
GND |8 9| B0
+----------+
4066
Quad analog switches.
+---+--+---+
1X |1 +--+ 14| VCC
1Y |2 13| 1EN
2Y |3 12| 4EN
2X |4 4016 11| 4X
2EN |5 4066 10| 4Y
3EN |6 9| 3Y
GND |7 8| 3X
+----------+
4067
16-to-1 line analog multiplexer/demultiplexer.
+-----+--+-----+
Y |1 +--+ 24| VCC
X7 |2 23| X8
X6 |3 22| X9
X5 |4 21| X10
X4 |5 20| X11
X3 |6 19| X12
X2 |7 4067 18| X13
X1 |8 17| X14
X0 |9 16| X15
S0 |10 15| /EN
S1 |11 14| S2
GND |12 13| S3
+--------------+
4068
8-input AND/NAND gate with complementary outputs.
+---+--+---+
Y |1 +--+ 14| VCC Y = ABCDEFGH
A |2 13| /Y
B |3 12| H
C |4 4068 11| G
D |5 10| F
|6 9| E
GND |7 8|
+----------+
4069
Hex inverters.
+---+--+---+ +---*---+ _
1A |1 +--+ 14| VCC | A |/Y | /Y = A
/1Y |2 13| 6A +===*===+
2A |3 12| /6Y | 0 | 1 |
/2Y |4 4069 11| 5A | 1 | 0 |
3A |5 10| /5Y +---*---+
/3Y |6 9| 4A
GND |7 8| /4Y
+----------+
4070
Quad 2-input XOR gates.
+---+--+---+ +---+---*---+ _ _
1A |1 +--+ 14| VCC | A | B | Y | Y = A$B = (A.B)+(A.B)
1B |2 13| 4B +===+===*===+
1Y |3 12| 4A | 0 | 0 | 0 |
2Y |4 4070 11| 4Y | 0 | 1 | 1 |
2A |5 10| 3Y | 1 | 0 | 1 |
2B |6 9| 3B | 1 | 1 | 0 |
GND |7 8| 3A +---+---*---+
+----------+
4071
Quad 2-input OR gates.
+---+--+---+ +---+---*---+
1A |1 +--+ 14| VCC | A | B | Y | Y = A+B
1B |2 13| 4B +===+===*===+
/1Y |3 12| 4A | 0 | 0 | 0 |
/2Y |4 4071 11| /4Y | 0 | 1 | 1 |
2A |5 10| /3Y | 1 | 0 | 1 |
2B |6 9| 3B | 1 | 1 | 1 |
GND |7 8| 3A +---+---*---+
+----------+
4072
Dual 4-input OR gates.
+---+--+---+ +---+---+---+---*---+
1Y |1 +--+ 14| VCC | A | B | C | D |/Y | Y = A+B+C+D
1A |2 13| 2Y +===+===+===+===*===+
1B |3 12| 2D | 0 | 0 | 0 | 0 | 0 |
1C |4 4072 11| 2C | 0 | 0 | 0 | 1 | 1 |
1D |5 10| 2B | 0 | 0 | 1 | X | 1 |
|6 9| 2A | 0 | 1 | X | X | 1 |
GND |7 8| | 1 | X | X | X | 1 |
+----------+ +---+---+---+---*---+
4073
Triple 3-input AND gates.
+---+--+---+ +---+---+---*---+
1A |1 +--+ 14| VCC | A | B | C | Y | Y = ABC
1B |2 13| 3A +===+===+===*===+
2A |3 12| 3B | 0 | X | X | 0 |
2B |4 4073 11| 3C | 1 | 0 | X | 0 |
2C |5 10| 3Y | 1 | 1 | 0 | 0 |
2Y |6 9| 1Y | 1 | 1 | 1 | 1 |
GND |7 8| 1C +---+---+---*---+
+----------+
4075
Triple 3-input OR gates.
+---+--+---+ +---+---+---*---+
1A |1 +--+ 14| VCC | A | B | C | Y | Y = A+B+C
1B |2 13| 3A +===+===+===*===+
2A |3 12| 3B | 0 | 0 | 0 | 0 |
2B |4 4075 11| 3C | 0 | 0 | 1 | 1 |
2C |5 10| 3Y | 0 | 1 | X | 1 |
2Y |6 9| 1Y | 1 | X | X | 1 |
GND |7 8| 1C +---+---+---*---+
+----------+
4076
4-bit 3-state D flip-flop with reset, dual clock enables and dual output enables.
+---+--+---+
/OE1 |1 +--+ 16| VCC
/OE2 |2 15| RST
Q0 |3 14| D0
Q1 |4 13| D1
Q2 |5 4076 12| D2
Q3 |6 11| D3
CLK |7 10| /CLKEN1
GND |8 9| /CLKEN2
+----------+
4077
Quad 2-input XNOR gates.
+---+--+---+ +---+---*---+ _ _ _
1A |1 +--+ 14| VCC | A | B |/Y | Y = A$B = (A.B)+(A.B)
1B |2 13| 4B +===+===*===+
/1Y |3 12| 4A | 0 | 0 | 1 |
/2Y |4 4077 11| /4Y | 0 | 1 | 0 |
2A |5 10| /3Y | 1 | 0 | 0 |
2B |6 9| 3B | 1 | 1 | 1 |
GND |7 8| 3A +---+---*---+
+----------+
4078
8-input OR/NOR gate with complementary outputs.
+---+--+---+
Y |1 +--+ 14| VCC Y=A+B+C+D+E+F+G+H
A |2 13| /Y
B |3 12| H
C |4 4078 11| G
D |5 10| F
|6 9| E
GND |7 8|
+----------+
4081
Quad 2-input AND gates.
+---+--+---+ +---+---*---+
1A |1 +--+ 14| VCC | A | B | Y | Y = AB
1B |2 13| 4B +===+===*===+
1Y |3 12| 4A | 0 | 0 | 0 |
2Y |4 4081 11| 4Y | 0 | 1 | 0 |
2A |5 10| 3Y | 1 | 0 | 0 |
2B |6 9| 3B | 1 | 1 | 1 |
GND |7 8| 3A +---+---*---+
+----------+
4082
Dual 4-input AND gates.
+---+--+---+ +---+---+---+---*---+
1Y |1 +--+ 14| VCC | A | B | C | D | Y | Y = ABCD
1A |2 13| 2Y +===+===+===+===*===+
1B |3 12| 2D | 0 | X | X | X | 0 |
1C |4 4082 11| 2C | 1 | 0 | X | X | 0 |
1D |5 10| 2B | 1 | 1 | 0 | X | 0 |
|6 9| 2A | 1 | 1 | 1 | 0 | 0 |
GND |7 8| | 1 | 1 | 1 | 1 | 1 |
+----------+ +---+---+---+---*---+
4085
Dual 3-wide 2/1-input AND-NOR gates.
+---+--+---+ _______
1A |1 +--+ 14| VCC /Y = AB+CD+E
1B |2 13| 1D
/1Y |3 12| 1C
/2Y |4 4085 11| 1E
2A |5 10| 2E
2B |6 9| 2D
GND |7 8| 2C
+----------+
4086
6-wide 2/1-input AND-NOR gate.
+---+--+---+ ________________
A |1 +--+ 14| VCC /Y = AB+CD+EF+GH+J+/K
B |2 13| H
/Y |3 12| G
|4 4086 11| K
C |5 10| J
D |6 9| F
GND |7 8| E
+----------+
4089
4-bit synchronous binary rate multiplier.
+---+--+---+
Q15 |1 +--+ 16| VCC
D2 |2 15| D1
D3 |3 14| D0
SET |4 13| RST
/Q |5 4089 12| CASC
Q |6 11| CIN
COUT |7 10| STB
GND |8 9| CLK
+----------+
4093
Quad 2-input NAND gates with schmitt-trigger inputs.
0.9V typical input hysteresis at VCC=+5V and 2.3V at VCC=+10V.
+---+--+---+ +---+---*---+ __
1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB
1B |2 13| 4B +===+===*===+
/1Y |3 12| 4A | 0 | 0 | 1 |
/2Y |4 4093 11| /4Y | 0 | 1 | 1 |
2A |5 10| /3Y | 1 | 0 | 1 |
2B |6 9| 3B | 1 | 1 | 0 |
GND |7 8| 3A +---+---*---+
+----------+
4094
8-bit 3-state serial-in parallel-out shift register with output latches.
Q7′ is Q7 delayed by half a cycle (i.e. clocked on falling edge).
+---+--+---+
LE |1 +--+ 16| VCC
D |2 15| OE
CLK |3 14| Y4
Y0 |4 13| Y5
Y1 |5 4094 12| Y6
Y2 |6 11| Y7
Y3 |7 10| Q7
GND |8 9| Q7'
+----------+
4095
J-K flip-flop with triple ANDed J an K inputs, set and reset.
+---+--+---+ +--------+--------+---+---+---*---+---+
|1 +--+ 14| VCC |J1.J2.J3|K1.K2.K3|CLK|SET|RST| Q |/Q |
RST |2 13| SET +========+========+===+===+===*===+===+
J1 |3 12| CLK | X | X | X | 1 | 1 | 0 | 0 |
J2 |4 4095 11| K3 | X | X | X | 1 | 0 | 1 | 0 |
J3 |5 10| K2 | X | X | X | 0 | 1 | 0 | 1 |
/Q |6 9| K1 | 0 | 0 | / | 0 | 0 | - | - |
GND |7 8| Q | 0 | 1 | / | 0 | 0 | 0 | 1 |
+----------+ | 1 | 0 | / | 0 | 0 | 1 | 0 |
| 1 | 1 | / | 0 | 0 |/Q | Q |
| X | X |!/ | 0 | 0 | - | - |
+--------+--------+---+---+---*---+---+
4096
J-K flip-flop with triple ANDed J an K inputs (one inverted), set and reset.
+---+--+---+ +---------+---------+---+---+---*---+---+
|1 +--+ 14| VCC |J1.J2./J3|K1.K2./K3|CLK|SET|RST| Q |/Q |
RST |2 13| SET +=========+=========+===+===+===*===+===+
J1 |3 12| CLK | X | X | X | 1 | 1 | 0 | 0 |
J2 |4 4096 11| K1 | X | X | X | 1 | 0 | 1 | 0 |
/J3 |5 10| K2 | X | X | X | 0 | 1 | 0 | 1 |
/Q |6 9| /K3 | 0 | 0 | / | 0 | 0 | - | - |
GND |7 8| Q | 0 | 1 | / | 0 | 0 | 0 | 1 |
+----------+ | 1 | 0 | / | 0 | 0 | 1 | 0 |
| 1 | 1 | / | 0 | 0 |/Q | Q |
| X | X |!/ | 0 | 0 | - | - |
+---------+---------+---+---+---*---+---+
4097
16-to-2 line analog multiplexer/demultiplexer.
+-----+--+-----+
1Y |1 +--+ 24| VCC
1X7 |2 23| 2X0
1X6 |3 22| 2X1
1X5 |4 21| 2X2
1X4 |5 20| 2X3
1X3 |6 19| 2X4
1X2 |7 4097 18| 2X5
1X1 |8 17| 2Y
1X0 |9 16| 2X6
S0 |10 15| 2X7
S1 |11 14| S2
GND |12 13| /EN
+--------------+
4098
Dual monostable multivibrator, retriggerable, resettable.
+---+--+---+
1Cext |1 +--+ 16| VCC
1RCext |2 15| 2Cext
1RST |3 14| 2RCext
1TR |4 13| 2RST
/1TR |5 4098 12| 2TR
1Q |6 11| /2TR
/1Q |7 10| 2Q
GND |8 9| /2Q
+----------+
4099
1-of-8 addressable latch with reset.
+---+--+---+
Q7 |1 +--+ 16| VCC
RST |2 15| Q6
D |3 14| Q5
/WR |4 13| Q4
A0 |5 4099 12| Q3
A1 |6 11| Q2
A2 |7 10| Q1
GND |8 9| Q0
+----------+
4316
Quad analog switches with enable input and dual power supply.
VEE supply may not be more positive than GND.
+---+--+---+
1X |1 +--+ 16| VCC
1Y |2 15| 1EN
2Y |3 14| 4EN
2X |4 13| 4X2
EN |5 4316 12| 4Y3
EN |6 11| 3Y
EN |7 10| 3X
GND |8 9| VEE
+----------+
4351
8-to-1 line analog multiplexer/demultiplexer with address latch and dualpower supply.
VEE supply may not be more positive than GND.
+---+--+---+
1X0 |1 +--+ 18| VCC
1X1 |2 17| X2
2X1 |3 16| X1
2Y |4 15| X0
2X0 |5 4351 14| X3
/EN |6 13| S0
EN |7 12| S1
VEE |8 11| S2
GND |9 10| LE
+----------+
4352
8-to-2 line analog multiplexer/demultiplexer with address latch and dualpower supply.
VEE supply may not be more positive than GND.
+---+ +---+
1X0 |1 +--+ 18| VCC
1X2 |2 17| 2X2
1Y |3 16| 2X1
1X3 |4 15| 2Y
1X1 |5 4352 14| 2X0
/EN |6 13| 2X3
EN |7 12| S0
VEE |8 11| S1
GND |9 10| LE
+----------+
4353
Triple 2-to-1 line analog multiplexer/demultiplexer with address latch anddual power supply.
VEE supply may not be more positive than GND.
+---+ +---+
1X0 |1 +--+ 18| VCC
1X1 |2 17| 1Y
2X1 |3 16| 3Y
2Y |4 15| 3X1
2X0 |5 4353 14| 3X0
/EN |6 13| 3S
EN |7 12| 1S
VEE |8 11| 2S
GND |9 10| LE
+----------+
4500
Industrial Control Unit.
If you _really_ want to use this RRRRISC, try to get the ‘MC14500B IndustrialControl Unit Handbook’ from Motorola (sorry, no ISBN number).
+---+ +---+
RST |1 +--+ 16| VCC
WR |2 15| RR
D |3 14| X0
I3 |4 13| X1
I2 |5 4500 12| JMP
I1 |6 11| RTN
I0 |7 10| FLG0
GND |8 9| FLGF
+----------+
4502
6-bit 3-state inverting buffer/line driver with NOR inputs.
+---+ +---+ +---+---+---+---+
A0 |1 +--+ 16| VCC |/OE| A | B I/Y |
/Y0 |2 15| A5 +===+===+===+===+
A1 |3 14| /Y5 | 1 | X | X I Z |
/OE |4 13| A4 | 0 | 0 | 0 I 1 |
/Y1 |5 4502 12| B | 0 | 1 | 0 I 0 |
A2 |6 11| /Y4 | 0 | X | 1 I 0 |
/Y2 |7 10| A3 +---+---+---+---+
GND |8 9| /Y3
+----------+
4503
2/4-bit 3-state noninverting buffer/line driver.
+---+ +---+ +---+---+---+
/1OE |1 +--+ 16| VCC |/OE| A I Y |
1A1 |2 15| /2OE +===+===+===+
1Y1 |3 14| 2A2 | 1 | X I Z |
1A2 |4 13| 2Y2 | 0 | 0 I 0 |
1Y2 |5 4503 12| 2A1 | 0 | 1 I 1 |
1A3 |6 11| 2Y1 +---+---+---+
1Y3 |7 10| 1A4
GND |8 9| 1Y4
+----------+
4508
Dual 4-bit 3-state transparent latch with reset.
+-----+ +-----+ +---+---+---+---+
1RST |1 +--+ 24| VCC |/OE| LE| D I Q |
1LE |2 23| 2Q3 +===+===+===+===+
/1OE |3 22| 2D3 | 1 | X | X I Z |
1D0 |4 21| 2Q2 | 0 | 0 | X I - |
1Q0 |5 20| 2D2 | 0 | 1 | 0 I 0 |
1D1 |6 19| 2Q1 | 0 | 1 | 1 I 1 |
1Q1 |7 4508 18| 2D1 +---+---+---+---+
1D2 |8 17| 2Q0
1Q2 |9 16| 2D0
1D3 |10 15| /2OE
1Q3 |11 14| 2LE
GND |12 13| 2RST
+--------------+
4510
4-bit synchronous decade up/down counter with asynchronous load, reset andripple carry output.
+---+ +---+
LD |1 +--+ 16| VCC
Q3 |2 15| CLK
P3 |3 14| Q2
P0 |4 13| P2
/RCI |5 4510 12| P1
Q0 |6 11| Q1
/RCO |7 10| UP//DN
GND |8 9| RST
+----------+
4512
8-to-1 line 3-state data selector/multiplexer with AND inputs.
+---+ +---+
A0 |1 +--+ 16| VCC Y = An./B
A1 |2 15| /OE
A2 |3 14| Y
A3 |4 13| S2
A4 |5 4512 12| S1
A5 |6 11| S0
A6 |7 10| /B
GND |8 9| A7
+----------+
4514
1-of-16 noninverting decoder/demultiplexer with address latches.
+---+ +---+
LE |1 +--+ 24| VCC
S0 |2 23| /EN
S1 |3 22| S3
Y7 |4 21| S2
Y6 |5 20| Y10
Y5 |6 19| Y11
Y4 |7 4514 18| Y8
Y3 |8 17| Y9
Y2 |9 16| Y15
Y1 |10 15| Y14
Y0 |11 14| Y13
GND |12 13| Y12
+----------+
4516
4-bit synchronous binary up/down counter with asynchronous load, reset andripple carry output.
+---+ +---+
LD |1 +--+ 16| VCC
Q3 |2 15| CLK
P3 |3 14| Q2
P0 |4 13| P2
/RCI |5 4516 12| P1
Q0 |6 11| Q1
/RCO |7 10| UP//DN
GND |8 9| RST
+----------+
4518
Dual 4-bit asynchronous decade counters with reset and both active high andactive low clocks.
+---+ +---+
1CLK |1 +--+ 16| VCC
/1CLK |2 15| 2RST
1Q0 |3 14| 2Q3
1Q1 |4 13| 2Q2
1Q2 |5 4518 12| 2Q1
1Q3 |6 11| 2Q0
1RST |7 10| /2CLK
GND |8 9| 2CLK
+----------+
4521
24-bit asynchronous binary counter with oscillator and res For the buffer to be used, GND’ et input,and one CMOS buffer with separate power supply.
Q0…Q17 outputs are missing. and VCC’must be connected to GND and VCC (optionally using series resistors).
+---+ +---+ +---+---+
Q24 |1 +--+ 16| VCC | A I Y |
RST |2 15| Q23 +===+===+
GND' |3 14| Q22 | 0 I 0 |
Y |4 13| Q21 | 1 I 1 |
VCC' |5 4521 12| Q20 +---+---+
A |6 11| Q19
X0 |7 10| Q18
GND |8 9| X1
+----------+
4527
4-bit synchronous decade rate multiplier.
+---+ +---+
Q9 |1 +--+ 16| VCC
D2 |2 15| D1
D3 |3 14| D0
SET9 |4 13| RST
/Q |5 4527 12| CASC
Q |6 11| CIN
COUT |7 10| STB
GND |8 9| CLK
+----------+
4532
8-to-3 line noninverting priority encoder with cascade inputs.
+---+ +---+
A4 |1 +--+ 16| VCC
A5 |2 15| EO
A6 |3 14| GS
A7 |4 13| A3
EI |5 4532 12| A2
Y2 |6 11| A1
Y1 |7 10| A0
GND |8 9| Y0
+----------+
4536
24-bit programmable frequency divider/digital timer with oscillator,set and reset inputs. Digitally programmable from 2^1 to 2^24.
Connect MONO via a >10k resistor to ground for square wave output,or to a RC network (R to VCC) for a controlled output pulse width.Maximum guaranteed clock frequency is a pitiful 500kHz.
+---+ +---+
SET |1 +--+ 16| VCC
RST |2 15| MONO
X1 |3 14| /XEN
X0 |4 13| Q
X2 |5 4536 12| S3
/DIV256 |6 11| S2
CLKEN |7 10| S1
GND |8 9| S0
+----------+
4538
Dual precision monostable multivibrator with Schmitt-trigger inputs.
Retriggerable, resettable.For 74HC4538 the Cext pins may be grounded.
+---+ +---+
1Cext |1 +--+ 16| VCC
1RCext |2 15| 2Cext
1RST |3 14| 2RCext
1TR |4 13| 2RST
/1TR |5 4538 12| 2TR
1Q |6 11| /2TR
/1Q |7 10| 2Q
GND |8 9| /2Q
+----------+
4543
BCD to 7-segment decoder/LCD driver with input latch.
The P (phase) input should be connected to the backplane of the LCD.
+---+ +---+
LE |1 +--+ 16| VCC
A2 |2 15| YF
A1 |3 14| YG
A3 |4 13| YE
A0 |5 4543 12| YD
@ |6 11| YC
BI |7 10| YB
GND |8 9| YA
+----------+
4555
Dual 1-of-4 noninverting decoder/demultiplexer.
+---+ +---+ +---+---+---+---+---+---+---+
/1EN |1 +--+ 16| VCC |/EN| S1| S0I Y0| Y1| Y2| Y3|
1S0 |2 15| /2EN +===+===+===+===+===+===+===+
1S1 |3 14| 2S0 | 1 | X | X I 0 | 0 | 0 | 0 |
1Y0 |4 13| 2S1 | 0 | 0 | 0 I 1 | 0 | 0 | 0 |
1Y1 |5 4555 12| 2Y0 | 0 | 0 | 1 I 0 | 1 | 0 | 0 |
1Y2 |6 11| 2Y1 | 0 | 1 | 0 I 0 | 0 | 1 | 0 |
1Y3 |7 10| 2Y2 | 0 | 1 | 1 I 0 | 0 | 0 | 1 |
GND |8 9| 2Y3 +---+---+---+---+---+---+---+
+----------+
4556
Dual 1-of-4 inverting decoder/demultiplexer.
+---+ +---+ +---+---+---+---+---+---+---+
/1EN |1 +--+ 16| VCC |/EN| S1| S0I/Y0|/Y1|/Y2|/Y3|
1S0 |2 15| /2EN +===+===+===+===+===+===+===+
1S1 |3 14| 2S0 | 1 | X | X I 1 | 1 | 1 | 1 |
/1Y0 |4 13| 2S1 | 0 | 0 | 0 I 0 | 1 | 1 | 1 |
/1Y1 |5 4556 12| /2Y0 | 0 | 0 | 1 I 1 | 0 | 1 | 1 |
/1Y2 |6 11| /2Y1 | 0 | 1 | 0 I 1 | 1 | 0 | 1 |
/1Y3 |7 10| /2Y2 | 0 | 1 | 1 I 1 | 1 | 1 | 0 |
GND |8 9| /2Y3 +---+---+---+---+---+---+---+
+----------+
4580
4×4-bit 3-state synchronous triple-port register file.
+-----+--+-----+
1Q3 |1 +--+ 24| VCC
1Q2 |2 23| 1Q1
1RD |3 22| 1Q0
2Q0 |4 21| 2RD
2Q1 |5 20| D0
2Q2 |6 19| D1
2Q3 |7 40108 18| D2
WA0 |8 17| D3
WA1 |9 16| WCLK
2RA1 |10 15| WR
2RA0 |11 14| 1RA1
GND |12 13| 1RA0
+--------------+
4585
4-bit noninverting magnitude comparator with cascade inputs.
+---+ +---+
B2 |1 +--+ 16| VCC
A2 |2 15| A3
OA=B |3 14| B3
IA>B |4 13| OA>B
IA<B |5 4585 12| OA<B
IA=B |6 11| B0
A1 |7 10| A0
GND |8 9| B1
+----------+
4599
1-of-8 addressable latch with readback and reset.
+---+ +---+
Q7 |1 +--+ 18| VCC
RST |2 17| Q6
D |3 16| Q5
/WR |4 15| Q4
A0 |5 4599 14| Q3
A1 |6 13| Q2
A2 |7 12| Q1
CE |8 11| Q0
GND |9 10| /RD
+----------+
14500
Industrial Control Unit.
If you _really_ want to use this RRRRISC, try to get the ‘MC14500B IndustrialControl Unit Handbook’ from Motorola (sorry, no ISBN number).
+---+--+---+
RST |1 +--+ 16| VCC
WR |2 15| RR
D |3 14| X0
I3 |4 13| X1
I2 |5 4500 12| JMP
I1 |6 11| RTN
I0 |7 10| FLG0
GND |8 9| FLGF
+----------+
40108
4×4-bit 3-state synchronous triple-port register file.
+-----+--+-----+
1Q3 |1 +--+ 24| VCC
1Q2 |2 23| 1Q1
1RD |3 22| 1Q0
2Q0 |4 21| 2RD
2Q1 |5 20| D0
2Q2 |6 19| D1
2Q3 |7 40108 18| D2
WA0 |8 17| D3
WA1 |9 16| WCLK
2RA1 |10 15| WR
2RA0 |11 14| 1RA1
GND |12 13| 1RA0
+--------------+
40208
4×4-bit 3-state synchronous triple-port register file.
+-----+--+-----+
1Q3 |1 +--+ 24| VCC
1Q2 |2 23| 1Q1
1RD |3 22| 1Q0
2Q0 |4 21| 2RD
2Q1 |5 20| D0
2Q2 |6 19| D1
2Q3 |7 40108 18| D2
WA0 |8 17| D3
WA1 |9 16| WCLK
2RA1 |10 15| WR
2RA0 |11 14| 1RA1
GND |12 13| 1RA0
+--------------+
4580
4×4-bit 3-state synchronous triple-port register file.
+-----+--+-----+
1Q3 |1 +--+ 24| VCC
1Q2 |2 23| 1Q1
1RD |3 22| 1Q0
2Q0 |4 21| 2RD
2Q1 |5 20| D0
2Q2 |6 19| D1
2Q3 |7 40108 18| D2
WA0 |8 17| D3
WA1 |9 16| WCLK
2RA1 |10 15| WR
2RA0 |11 14| 1RA1
GND |12 13| 1RA0
+--------------+
40100
32-bit bidirectional serial-in serial-out shift register with two AND gated clocks.
With /LOOP input low, data is rotated and serial data input ignored.
+---+--+---+
|1 +--+ 16| VCC
/CLK2 |2 15|
CLK1 |3 14|
Q0 |4 13| L//R
|5 40100 12| Q31
L |6 11| D
|7 10|
GND |8 9| /LOOP
+----------+
40101
9-bit odd/even parity generator/checker.
+---+--+---+
A0 |1 +--+ 14| VCC
A1 |2 13| A8
A2 |3 12| A7
A3 |4 40101 11| A6
A4 |5 10| A5
ODD |6 9| EVEN
GND |7 8| /EN
+----------+
40102
8-bit (2-digit) synchronous decade down counter with synchronous and asynchronous load and reset. Counter outputs only internally connected but ripple carry and zero detect outputs available.
+---+--+---+
CLK |1 +--+ 16| VCC
/RST |2 15| /SLD
/CLKEN |3 14| /RCO
P0 |4 13| P7
P1 |5 40102 12| P6
P2 |6 11| P5
P3 |7 10| P4
GND |8 9| /ALD
+----------+
40103
8-bit synchronous binary down counter with synchronous and asynchronous load and reset. Counter outputs only internally connected but ripple carry and zero detect outputs available.
+---+--+---+
CLK |1 +--+ 16| VCC
/RST |2 15| /SLD
/CLKEN |3 14| /RCO
P0 |4 13| P7
P1 |5 40103 12| P6
P2 |6 11| P5
P3 |7 10| P4
GND |8 9| /ALD
+----------+
40104
4-bit 3-state bidirectional universal shift register.
+---+--+---+ +---+---*---------------+
OE |1 +--+ 16| VCC | S1| S0| Function |
D |2 15| Y0 +===+===*===============+
P0 |3 14| Y1 | 0 | 0 | Reset |
P1 |4 13| Y2 | 0 | 1 | Shift right |
P2 |5 40104 12| Y3 | 1 | 0 | Shift left |
P3 |6 11| CLK | 1 | 1 | Parallel load |
L |7 10| S1 +---+---*---------------+
GND |8 9| S0
+----------+
40105
16×4 3-state asynchronous FIFO with reset.
+---+--+---+
OE |1 +--+ 16| VCC
/FULL |2 15| RD
WR |3 14| /EMPTY
D0 |4 13| Q0
D1 |5 40105 12| Q1
D2 |6 11| Q2
D3 |7 10| Q3
GND |8 9| RST
+----------+
40106
Hex inverters with schmitt-trigger inputs.
0.9V typical input hysteresis at VCC=+5V and 2.3V at VCC=+10V.
+---+--+---+ +---*---+ _
1A |1 +--+ 14| VCC | A |/Y | /Y = A
/1Y |2 13| 6A +===*===+
2A |3 12| /6Y | 0 | 1 |
/2Y |4 40106 11| 5A | 1 | 0 |
3A |5 10| /5Y +---*---+
/3Y |6 9| 4A
GND |7 8| /4Y
+----------+
40107
Dual 2-input open-collector NAND gates with buffered output.
+---+--+---+ +---+---*---+ __
1A |1 +--+ 8| VCC | A | B |/Y | /Y = AB
1B |2 7| 2B +===+===*===+
/1Y |3 40107 6| 2A | 0 | 0 | Z |
GND |4 5| /2Y | 0 | 1 | Z |
+----------+ | 1 | 0 | Z |
| 1 | 1 | 0 |
+---+---*---+
40108
4×4-bit 3-state synchronous triple-port register file.
+-----+--+-----+
1Q3 |1 +--+ 24| VCC
1Q2 |2 23| 1Q1
1RD |3 22| 1Q0
2Q0 |4 21| 2RD
2Q1 |5 20| D0
2Q2 |6 19| D1
2Q3 |7 40108 18| D2
WA0 |8 17| D3
WA1 |9 16| WCLK
2RA1 |10 15| WR
2RA0 |11 14| 1RA1
GND |12 13| 1RA0
+--------------+
40109
Quad 3-state noninverting buffer/level shifter.
VDD supplies the output stage, VCC the input stage.
+---+--+---+ +---+---*-----+
VCC |1 +--+ 16| VDD | A | OE| Y |
1OE |2 15| 4OE +===+===*=====+
1A |3 14| 4A | X | 0 | Z |
1Y |4 13| 4Y | 0 | 1 | GND |
2Y |5 40109 12| | 1 | 1 | VDD |
2A |6 11| 3Y +---+---*-----+
2OE |7 10| 3A
GND |8 9| 3OE
+----------+
40110
4-bit asynchronous decade up/down counter with 7-segment decoder/common- cathode LED driver, ripple carry and borrow, separate up and down clocks, clock enable and output latch.
+---+--+---+
YA |1 +--+ 16| VCC
YG |2 15| YB
YF |3 14| YC
/CLKEN |4 13| YD
RST |5 40110 12| YE
LE |6 11| BORROW
CLKDN |7 10| CARRY
GND |8 9| CLKUP
+----------+
40147
10-to-4 line noninverting priority encoder.
+---+--+---+
A4 |1 +--+ 16| VCC
A5 |2 15| A0
A6 |3 14| Y3
A7 |4 13| A3
A8 |5 40147 12| A2
Y2 |6 11| A1
Y1 |7 10| A9
GND |8 9| Y0
+----------+
40160
4-bit synchronous decade counter with load, asynchronous reset, and ripple carry output.
+---+--+---+
/RST |1 +--+ 16| VCC
CLK |2 15| RCO
P0 |3 14| Q0
P1 |4 74 13| Q1
P2 |5 160 12| Q2
P3 |6 11| Q3
ENP |7 10| ENT
GND |8 9| /LOAD
+----------+
40161
4-bit synchronous binary counter with load, asynchronous reset, and ripple carry output.
+---+--+---+
/RST |1 +--+ 16| VCC
CLK |2 15| RCO
P0 |3 14| Q0
P1 |4 74 13| Q1
P2 |5 161 12| Q2
P3 |6 11| Q3
ENP |7 10| ENT
GND |8 9| /LOAD
+----------+
40162
4-bit synchronous decade counter with load, reset, and ripple carry output.
+---+--+---+
/RST |1 +--+ 16| VCC
CLK |2 15| RCO
P0 |3 14| Q0
P1 |4 74 13| Q1
P2 |5 162 12| Q2
P3 |6 11| Q3
ENP |7 10| ENT
GND |8 9| /LOAD
+----------+
40163
4-bit synchronous binary counter with load, reset, and ripple carry output.
+---+--+---+
/RST |1 +--+ 16| VCC
CLK |2 15| RCO
P0 |3 14| Q0
P1 |4 74 13| Q1
P2 |5 163 12| Q2
P3 |6 11| Q3
ENP |7 10| ENT
GND |8 9| /LOAD
+----------+
40174
6-bit D flip-flop with reset.
+---+--+---+ +----+---+---*---+
/RST |1 +--+ 16| VCC |/RST|CLK| D | Q |
Q0 |2 15| Q6 +====+===+===*===+
D0 |3 14| D5 | 0 | X | X | 0 |
D1 |4 74 13| D4 | 1 | / | 0 | 0 |
Q1 |5 174 12| Q4 | 1 | / | 1 | 1 |
D2 |6 11| D3 | 1 |!/ | X | - |
Q2 |7 10| Q3 +----+---+---*---+
GND |8 9| CLK
+----------+
40181
4-bit 16-function arithmetic logic unit (ALU)
+---+--+---+
/B0 |1 +--+ 24| VCC
/A0 |2 23| /A1
S3 |3 22| /B1
S2 |4 21| /A2
S1 |5 20| /B2
S0 |6 74 19| /A3
CIN |7 181 18| /B3
M |8 17| /G
/F0 |9 16| COUT
/F1 |10 15| /P
/F2 |11 14| A=B
GND |12 13| /F3
+----------+
40182
Look-ahead carry generator Capable of anticipating a carry across four binary adders or group of adders.
Cascadable to perform full look-ahead across n-bit adders.
+---+--+---+
/G1 |1 +--+ 16| VCC
/P1 |2 15| /P2
/G0 |3 14| /G2
/P0 |4 74 13| Cn
/G3 |5 182 12| Cn+X
/P3 |6 11| Cn+Y
/P |7 10| /G
GND |8 9| Cn+Z
+----------+
40192
4-bit synchronous decade up/down counter with asynchronous load and reset, and separate up and down clocks, carry and borrow outputs.
+---+--+---+
P1 |1 +--+ 16| VCC
Q1 |2 15| P0
Q0 |3 14| RST
DOWN |4 74 13| /BORROW
UP |5 192 12| /CARRY
Q2 |6 11| /LOAD
Q3 |7 10| P2
GND |8 9| P3
+----------+
40193
4-bit synchronous binary up/down counter with asynchronous load and reset, and separate up and down clocks. Carry and borrow outputs.
+---+--+---+
P1 |1 +--+ 16| VCC
Q1 |2 15| P0
Q0 |3 14| RST
DOWN |4 74 13| /BORROW
UP |5 193 12| /CARRY
Q2 |6 11| /LOAD
Q3 |7 10| P2
GND |8 9| P3
+----------+
40194
4-bit bidirectional universal shift register with asynchronous reset.
+---+--+---+ +---+---*---------------+
/RST |1 +--+ 16| VCC | S1| S0| Function |
D |2 15| Q0 +===+===*===============+
P0 |3 14| Q1 | 0 | 0 | Hold |
P1 |4 40194 13| Q2 | 0 | 1 | Shift right |
P2 |5 74194 12| Q3 | 1 | 0 | Shift left |
P3 |6 11| CLK | 1 | 1 | Parallel load |
L |7 10| S1 +---+---*---------------+
GND |8 9| S0
+----------+
40208
4×4-bit 3-state synchronous triple-port register file.
+-----+--+-----+
1Q3 |1 +--+ 24| VCC
1Q2 |2 23| 1Q1
1RD |3 22| 1Q0
2Q0 |4 21| 2RD
2Q1 |5 20| D0
2Q2 |6 19| D1
2Q3 |7 40108 18| D2
WA0 |8 17| D3
WA1 |9 16| WCLK
2RA1 |10 15| WR
2RA0 |11 14| 1RA1
GND |12 13| 1RA0
+--------------+
40257
8-to-4 line 3-state noninverting data selector/multiplexer.
+---+--+---+
S |1 +--+ 16| VCC
1A0 |2 15| /EN
1A1 |3 14| 4A0
1Y |4 74 13| 4A1
2A0 |5 257 12| 4Y
2A1 |6 11| 3A0
2Y |7 10| 3A1
GND |8 9| 3Y
+----------+