{"id":302,"date":"2017-04-02T23:38:30","date_gmt":"2017-04-02T23:38:30","guid":{"rendered":"http:\/\/pcbjunkie.net\/?page_id=302"},"modified":"2017-04-02T23:40:04","modified_gmt":"2017-04-02T23:40:04","slug":"4000-series-ic-info-page","status":"publish","type":"page","link":"https:\/\/pcbjunkie.net\/index.php\/resources\/4000-series-ic-info-page\/","title":{"rendered":"4000 Series IC Info Page"},"content":{"rendered":"<h2>4000<\/h2>\n<p>Dual 3-input NOR gates and inverter.<\/p>\n<pre>    +---+--+---+                ________\r\n    |1  +--+ 14| VCC        \/1Y=1A+1B+1C\r\n    |2       13| 3C\r\n 1A |3       12| 3B             __\r\n 1B |4  4000 11| 3A         \/2Y=2A\r\n 1C |5       10| \/3Y\r\n\/1Y |6        9| \/2Y            ________\r\nGND |7        8| 2A         \/3Y=3A+3B+3C\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4001\"><\/a><\/p>\n<h2>4001<\/h2>\n<p>Quad 2-input NOR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+           ___\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = A+B\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3       12| 4A          | 0 | 0 | 1 |\r\n\/2Y |4  4001 11| \/4Y         | 0 | 1 | 0 |\r\n 2A |5       10| \/3Y         | 1 | 0 | 0 |\r\n 2B |6        9| 3B          | 1 | 1 | 0 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4002\"><\/a><\/p>\n<h2>4002<\/h2>\n<p>Dual 4-input NOR gates.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+       _________\r\n\/1Y |1  +--+ 14| VCC         | A | B | C | D |\/Y |  \/Y = (A+B+C+D)\r\n 1A |2       13| \/2Y         +===+===+===+===*===+\r\n 1B |3       12| 2D          | 0 | 0 | 0 | 0 | 1 |\r\n 1C |4  4002 11| 2C          | 0 | 0 | 0 | 1 | 0 |\r\n 1D |5       10| 2B          | 0 | 0 | 1 | X | 0 |\r\n    |6        9| 2A          | 0 | 1 | X | X | 0 |\r\nGND |7        8|             | 1 | X | X | X | 0 |\r\n    +----------+             +---+---+---+---*---+\r\n<\/pre>\n<p><a name=\"4006\"><\/a><\/p>\n<h2>4006<\/h2>\n<p>Dual 4-bit and dual 5-bit serial-in serial-out shift registers with common clock.<\/p>\n<pre>     +---+--+---+\r\n  1D |1  +--+ 14| VCC\r\n\/1Q4 |2       13| 1Q4\r\n CLK |3       12| 2Q5\r\n  2D |4  4006 11| 2Q4\r\n  3D |5       10| 3Q4\r\n  4D |6        9| 4Q5\r\n GND |7        8| 4Q4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4007\"><\/a><\/p>\n<h2>4007<\/h2>\n<p>Dual complementary CMOS pair and unbuffered inverter.<br \/>\nFor use as simple inverters, connect 1pS=3pS=VCC, 1nS=3nS=GND, 1pD=1nD=\/1Y and 2pD=2nD=\/2Y.<\/p>\n<pre>     +---+--+---+\r\n 1pD |1  +--+ 14| VCC\r\n 1pS |2       13| 2pD\r\n  1G |3       12| \/3Y\r\n 1nS |4  4007 11| 3pS\r\n 1nD |5       10| 3G\r\n  2G |6        9| 3nS\r\n GND |7        8| 2nD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4008\"><\/a><\/p>\n<h2>4008<\/h2>\n<p>4-bit binary full adder with fast carry.<\/p>\n<pre>    +---+--+---+\r\n A3 |1  +--+ 16| VCC         S=A+B+CIN\r\n B2 |2       15| B3\r\n A2 |3       14| CO\r\n B1 |4       13| S3\r\n A1 |5  4008 12| S2\r\n B0 |6       11| S1\r\n A0 |7       10| S0\r\nGND |8        9| CI\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4009\"><\/a><\/p>\n<h2>4009<\/h2>\n<p>Hex inverters with level shifted outputs.<br \/>\nVDD may not be lower than VCC.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\nVCC |1  +--+ 16| VDD         | A |\/Y |          \/Y = A\r\n\/Y1 |2       15| \/Y6         +===*===+\r\n A1 |3       14| A6          | 0 | 1 |\r\n\/Y2 |4       13|             | 1 | 0 |\r\n A2 |5  4009 12| \/Y5         +---*---+\r\n\/Y3 |6       11| A5\r\n A3 |7       10| \/Y4\r\nGND |8        9| A4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4010\"><\/a><\/p>\n<h2>4010<\/h2>\n<p>Hex buffers with level shifted outputs.<br \/>\nVDD may not be lower than VCC.<\/p>\n<pre>    +---+--+---+             +---*---+\r\nVCC |1  +--+ 16| VDD         | A | Y |           Y = A\r\n Y1 |2       15| Y6          +===*===+\r\n A1 |3       14| A6          | 0 | 0 |\r\n Y2 |4       13|             | 1 | 1 |\r\n A2 |5  4010 12| Y5          +---*---+\r\n Y3 |6       11| A5\r\n A3 |7       10| Y4\r\nGND |8        9| A4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4011\"><\/a><\/p>\n<h2>4011<\/h2>\n<p>Quad 2-input NAND gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3       12| 4A          | 0 | 0 | 1 |\r\n\/2Y |4  4011 11| \/4Y         | 0 | 1 | 1 |\r\n 2A |5       10| \/3Y         | 1 | 0 | 1 |\r\n 2B |6        9| 3B          | 1 | 1 | 0 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4012\"><\/a><\/p>\n<h2>4012<\/h2>\n<p>Dual 4-input NAND gates.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+        ____\r\n\/1Y |1  +--+ 14| VCC         | A | B | C | D |\/Y |   \/Y = ABCD\r\n 1A |2       13| \/2Y         +===+===+===+===*===+\r\n 1B |3       12| 2D          | 0 | X | X | X | 1 |\r\n 1C |4  4012 11| 2C          | 1 | 0 | X | X | 1 |\r\n 1D |5       10| 2B          | 1 | 1 | 0 | X | 1 |\r\n    |6        9| 2A          | 1 | 1 | 1 | 0 | 1 |\r\nGND |7        8|             | 1 | 1 | 1 | 1 | 0 |\r\n    +----------+             +---+---+---+---*---+\r\n<\/pre>\n<p><a name=\"4013\"><\/a><\/p>\n<h2>4013<\/h2>\n<p>Dual D flip-flop with set and reset.<\/p>\n<pre>      +---+--+---+           +---+---+---+---*---+---+\r\n   1Q |1  +--+ 14| VCC       | D |CLK|SET|RST| Q |\/Q |\r\n  \/1Q |2       13| 2Q        +===+===+===+===*===+===+\r\n 1CLK |3       12| \/2Q       | X | X | 0 | 1 | 0 | 1 |\r\n 1RST |4  4013 11| 2CLK      | X | X | 1 | 0 | 1 | 0 |\r\n   1D |5       10| 2RST      | X | X | 1 | 1 | 1 | 1 |\r\n 1SET |6        9| 2D        | 0 | \/ | 0 | 0 | 0 | 1 |\r\n  GND |7        8| 2SET      | 1 | \/ | 0 | 0 | 1 | 1 |\r\n      +----------+           | X |!\/ | 0 | 0 | - | - |\r\n                             +---+---+---+---*---+---+\r\n<\/pre>\n<p><a name=\"4014\"><\/a><\/p>\n<h2>4014<\/h2>\n<p>8-bit parallel-in serial-out shift register with three parallel outputs.<\/p>\n<pre>    +---+--+---+\r\n P7 |1  +--+ 16| VCC\r\n Q5 |2       15| P6\r\n Q7 |3       14| P5\r\n P3 |4       13| P4\r\n P2 |5  4014 12| Q6\r\n P1 |6       11| D\r\n P0 |7       10| CLK\r\nGND |8        9| LD\/\/SH\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4015\"><\/a><\/p>\n<h2>4015<\/h2>\n<p>Dual 4-bit serial-in parallel-out shift register with asynchronous reset.<\/p>\n<pre>     +---+--+---+\r\n2CLK |1  +--+ 16| VCC\r\n 2Q3 |2       15| 2D\r\n 1Q2 |3       14| 2RST\r\n 1Q1 |4       13| 2Q0\r\n 1Q0 |5  4015 12| 2Q1\r\n1RST |6       11| 2Q2\r\n  1D |7       10| 1Q3\r\n GND |8        9| 1CLK\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4016\"><\/a><\/p>\n<h2>4016<\/h2>\n<p>Quad analog switches.<\/p>\n<pre>     +---+--+---+\r\n  1X |1  +--+ 14| VCC\r\n  1Y |2       13| 1EN\r\n  2Y |3       12| 4EN\r\n  2X |4  4016 11| 4X\r\n 2EN |5  4066 10| 4Y\r\n 3EN |6        9| 3Y\r\n GND |7        8| 3X\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4017\"><\/a><\/p>\n<h2>4017<\/h2>\n<p>4-bit asynchronous decade counter with fully decoded outputs, reset and both active high and active low clocks.<\/p>\n<p>The two CLK inputs are ANDed together, so that either can be used as clock or clock enable.<\/p>\n<pre>    +---+--+---+\r\n Q5 |1  +--+ 16| VCC\r\n Q1 |2       15| RST\r\n Q0 |3       14| CLK1\r\n Q2 |4       13| \/CLK2\r\n Q6 |5  4017 12| RCO\r\n Q7 |6       11| Q9\r\n Q3 |7       10| Q4\r\nGND |8        9| Q8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4018\"><\/a><\/p>\n<h2>4018<\/h2>\n<p>5-stage (divide by 2,4,6,8 or 10) Johnson counter with preset inputs.<\/p>\n<pre>    +---+--+---+\r\n  D |1  +--+ 16| VCC\r\n P1 |2       15| RST\r\n P2 |3       14| CLK\r\n\/Q2 |4       13| \/Q5\r\n\/Q1 |5  4018 12| P5\r\n\/Q3 |6       11| \/Q4\r\n P3 |7       10| PE\r\nGND |8        9| P4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4019\"><\/a><\/p>\n<h2>4019<\/h2>\n<p>8-to-4 line noninverting data selector\/multiplexer with OR function.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+\r\n4A1 |1  +--+ 16| VCC         | A0| A1| S1| S0| Y |    Y=S0.A0+S1.A1\r\n3A0 |2       15| 4A0         +===+===+===+===*===+\r\n3A1 |3       14| S1          | X | X | 0 | 0 | 0 |\r\n2A0 |4       13| Y4          | X | 0 | 0 | 1 | 0 |\r\n2A1 |5  4019 12| Y3          | 0 | X | 1 | 0 | 0 |\r\n1A0 |6       11| Y2          | X | 1 | X | 1 | 1 |\r\n1A1 |7       10| Y1          | 1 | X | 1 | X | 1 |\r\nGND |8        9| S0          +---+---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4020\"><\/a><\/p>\n<h2>4020<\/h2>\n<p>14-bit asynchronous binary counter with reset.<br \/>\nQ1 and Q2 outputs missing.<\/p>\n<pre>    +---+--+---+\r\nQ11 |1  +--+ 16| VCC\r\nQ12 |2       15| Q10\r\nQ13 |3       14| Q9\r\n Q5 |4       13| Q7\r\n Q4 |5  4020 12| Q8\r\n Q6 |6       11| RST\r\n Q3 |7       10| \/CLK\r\nGND |8        9| Q0\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4021\"><\/a><\/p>\n<h2>4021<\/h2>\n<p>8-bit parallel-in serial-out shift register with asynchronous load input and three parallel outputs.<\/p>\n<pre>    +---+--+---+\r\n P7 |1  +--+ 16| VCC\r\n Q5 |2       15| P6\r\n Q7 |3       14| P5\r\n P3 |4       13| P4\r\n P2 |5  4021 12| Q6\r\n P1 |6       11| D\r\n P0 |7       10| CLK\r\nGND |8        9| LD\/\/SH\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4022\"><\/a><\/p>\n<h2>4022<\/h2>\n<p>3-bit asynchronous binary counter with fully decoded outputs, reset and both active high and active low clocks.<\/p>\n<p>The two CLK inputs are ANDed together, so that either can be used as clock or clock enable.<\/p>\n<pre>    +---+--+---+\r\n Q1 |1  +--+ 16| VCC\r\n Q0 |2       15| RST\r\n Q2 |3       14| CLK1\r\n Q5 |4       13| \/CLK2\r\n Q6 |5  4022 12| RCO\r\n    |6       11| Q4\r\n Q3 |7       10| Q7\r\nGND |8        9|\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4023\"><\/a><\/p>\n<h2>4023<\/h2>\n<p>Triple 3-input NAND gates.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+       ___\r\n 1A |1  +--+ 14| VCC         | A | B | C |\/Y |  \/Y = ABC\r\n 1B |2       13| 3C          +===+===+===*===+\r\n 2A |3       12| 3B          | 0 | X | X | 1 |\r\n 2B |4  4023 11| 3A          | 1 | 0 | X | 1 |\r\n 2C |5       10| \/3Y         | 1 | 1 | 0 | 1 |\r\n\/2Y |6        9| \/1Y         | 1 | 1 | 1 | 0 |\r\nGND |7        8| 1C          +---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4024\"><\/a><\/p>\n<h2>4024<\/h2>\n<p>7-bit asynchronous binary counter with reset.<\/p>\n<pre>     +---+--+---+\r\n\/CLK |1  +--+ 14| VCC\r\n RST |2       13|\r\n  Q6 |3       12| Q0\r\n  Q5 |4  4024 11| Q1\r\n  Q4 |5       10|\r\n  Q3 |6        9| Q2\r\n GND |7        8|\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4025\"><\/a><\/p>\n<h2>4025<\/h2>\n<p>Triple 3-input NOR gates.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+       _____\r\n 1A |1  +--+ 14| VCC         | A | B | C |\/Y |  \/Y = A+B+C\r\n 1B |2       13| 3C          +===+===+===*===+\r\n 2A |3       12| 3B          | 0 | 0 | 0 | 1 |\r\n 2B |4  4025 11| 3A          | 0 | 0 | 1 | 0 |\r\n 2C |5       10| \/3Y         | 0 | 1 | X | 0 |\r\n\/2Y |6        9| \/1Y         | 1 | X | X | 0 |\r\nGND |7        8| 1C          +---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4026\"><\/a><\/p>\n<h2>4026<\/h2>\n<p>4-bit asynchronous decade counter with 7-segment decoder\/common-cathode LED driver, display enable, ripple carry, reset and both active high and active low clocks.<\/p>\n<pre>      +---+--+---+\r\n CLK1 |1  +--+ 16| VCC\r\n\/CLK2 |2       15| RST\r\n  DEI |3       14| YC'\r\n  DEO |4       13| YC\r\n   CO |5  4026 12| YB\r\n   YF |6       11| YE\r\n   YG |7       10| YA\r\n  GND |8        9| YD\r\n      +----------+\r\n<\/pre>\n<p><a name=\"4027\"><\/a><\/p>\n<h2>4027<\/h2>\n<p>Dual J-K flip-flops with set and reset.<\/p>\n<pre>      +---+--+---+           +---+---+---+---+---*---+---+\r\n   1Q |1  +--+ 16| VCC       | J | K |CLK|SET|RST| Q |\/Q |\r\n  \/1Q |2       15| 2Q        +===+===+===+===+===*===+===+\r\n 1CLK |3       14| \/2Q       | X | X | X | 1 | 1 | 1 | 1 |\r\n 1RST |4       13| 2CLK      | X | X | X | 1 | 0 | 1 | 0 |\r\n   1K |5  4027 12| 2RST      | X | X | X | 0 | 1 | 0 | 1 |\r\n   1J |6       11| 2K        | 0 | 0 | \/ | 0 | 0 | - | - |\r\n 1SET |7       10| 2J        | 0 | 1 | \/ | 0 | 0 | 0 | 1 |\r\n  GND |8        9| 2SET      | 1 | 0 | \/ | 0 | 0 | 1 | 0 |\r\n      +----------+           | 1 | 1 | \/ | 0 | 0 |\/Q | Q |\r\n                             | X | X |!\/ | 0 | 0 | - | - |\r\n                             +---+---+---+---+---*---+---+\r\n<\/pre>\n<p><a name=\"4028\"><\/a><\/p>\n<h2>4028<\/h2>\n<p>1-of-10 noninverting decoder\/demultiplexer.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+---+---+---+\r\n Y4 |1  +--+ 16| VCC         | S3| S2| S1| S0| Y0| Y1|...| Y9|\r\n Y2 |2       15| Y3          +===+===+===+===*===+===+===+===+\r\n Y0 |3       14| Y1          | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |\r\n Y7 |4       13| S1          | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |\r\n Y9 |5  4028 12| S2          | . | . | . | . | 0 | 0 | . | 0 |\r\n Y5 |6       11| S3          | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |\r\n Y6 |7       10| S0          | 1 | 0 | 1 | X | 0 | 0 | 0 | 0 |\r\nGND |8        9| Y8          | 1 | 1 | X | X | 0 | 0 | 0 | 0 |\r\n    +----------+             +---+---+---+---*---+---+---+---+\r\n<\/pre>\n<p><a name=\"4029\"><\/a><\/p>\n<h2>4029<\/h2>\n<p>4-bit synchronous binary\/decade up\/down counter with preset and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\n  PE |1  +--+ 16| VCC\r\n  Q4 |2       15| CLK\r\n  P4 |3       14| Q3\r\n  P1 |4       13| P3\r\n\/RCI |5  4029 12| P2\r\n  Q1 |6       11| Q2\r\n\/RCO |7       10| U\/\/D\r\n GND |8        9| B\/\/D\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4030\"><\/a><\/p>\n<h2>4030<\/h2>\n<p>Quad 2-input XOR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+                    _   _\r\n 1A |1  +--+ 14| VCC         | A | B | Y |       Y = A$B = (A.B)+(A.B)\r\n 1B |2       13| 4B          +===+===*===+\r\n 1Y |3       12| 4A          | 0 | 0 | 0 |\r\n 2Y |4  4030 11| 4Y          | 0 | 1 | 1 |\r\n 2A |5       10| 3Y          | 1 | 0 | 1 |\r\n 2B |6        9| 3B          | 1 | 1 | 0 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4031\"><\/a><\/p>\n<h2>4031<\/h2>\n<p>64-bit serial-in serial-out shift register with multiplexed inputs.<br \/>\nY is Q63 delayed by half a cycle (i.e. clocked on falling edge).<\/p>\n<pre>     +---+--+---+\r\n   E |1  +--+ 16| VCC\r\n CLK |2       15| D\r\n     |3       14|\r\n     |4       13|\r\n   Y |5  4031 12|\r\n Q63 |6       11|\r\n\/Q63 |7       10| E\/\/D\r\n GND |8        9| CLKout\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4032\"><\/a><\/p>\n<h2>4032<\/h2>\n<p>Triple serial adder.<br \/>\nEach section can be used to add long binary words, one bit on each clock cycle. CRST resets the internal carry flip-flop after one clock delay. The INV inputs can be used to invert the sum output (giving a 1&#8217;s-complemented result).<\/p>\n<pre>     +---+--+---+\r\n  3S |1  +--+ 16| VCC\r\n3INV |2       15| 3A\r\n CLK |3       14| 3B\r\n  2S |4       13| 2A\r\n2INV |5  4032 12| 2B\r\nCRST |6       11| 1B\r\n1INV |7       10| 1A\r\n GND |8        9| 1S\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4033\"><\/a><\/p>\n<h2>4033<\/h2>\n<p>4-bit asynchronous decade counter with 7-segment decoder\/common-cathode LED driver, ripple blanking, ripple carry, reset and both active high and active low clocks.<\/p>\n<pre>      +---+--+---+\r\n CLK1 |1  +--+ 16| VCC\r\n\/CLK2 |2       15| RST\r\n  RBI |3       14| LT\r\n  RBO |4       13| YC\r\n   CO |5  4033 12| YB\r\n   YF |6       11| YE\r\n   YG |7       10| YA\r\n  GND |8        9| YD\r\n      +----------+\r\n<\/pre>\n<p><a name=\"4034\"><\/a><\/p>\n<h2>4034<\/h2>\n<p>8-bit bidirectional universal shift register with common serial input, dual parallel I\/O ports and selectable synchronous\/asynchronous parallel load.<\/p>\n<pre>     +-----+--+-----+             +------+--------+-------+-------+\r\n  A7 |1    +--+   24| VCC         | B\/\/A | LD\/\/SH | A0..7 | B0..7 |\r\n  A6 |2           23| B7          +======+========+=======+=======+\r\n  A5 |3           22| B6          |  0   |   1    |  in   |  out  |\r\n  A4 |4           21| B5          |  1   |   1    |  out  |  in   |\r\n  A3 |5           20| B4          |  0   |   0    |   Z   |  out  |\r\n  A2 |6           19| B3          |  1   |   0    |  out  |   Z   |\r\n  A1 |7    4034   18| B2          +------+--------+-------+-------+\r\n  A0 |8           17| B1\r\n ENA |9           16| B0\r\n   D |10          15| CLK\r\nB\/\/A |11          14| ASY\/\/SY\r\n GND |12          13| LD\/\/SH\r\n     +--------------+\r\n<\/pre>\n<p><a name=\"4035\"><\/a><\/p>\n<h2>4035<\/h2>\n<p>4-bit inverting\/noninverting universal shift register with J-\/K inputs and asynchronous reset.<\/p>\n<pre>       +---+--+---+\r\n    Q0 |1  +--+ 16| VCC\r\n  \/INV |2       15| Q1\r\n    \/K |3       14| Q2\r\n     J |4       13| Q3\r\n   RST |5  4035 12| P3\r\n   CLK |6       11| P2\r\nLD\/\/SH |7       10| P1\r\n   GND |8        9| P0\r\n       +----------+\r\n<\/pre>\n<p><a name=\"4038\"><\/a><\/p>\n<h2>4038<\/h2>\n<p>Triple negative-edge-triggered serial adder.<br \/>\nEach section can be used to add long binary words, one bit on each clock cycle. CRST resets the internal carry flip-flop after one clock delay. The INV inputs can be used to invert the sum output (giving a 1&#8217;s-complemented result).<\/p>\n<pre>     +---+--+---+\r\n  3S |1  +--+ 16| VCC\r\n3INV |2       15| 3A\r\n\/CLK |3       14| 3B\r\n  2S |4       13| 2A\r\n2INV |5  4038 12| 2B\r\nCRST |6       11| 1B\r\n1INV |7       10| 1A\r\n GND |8        9| 1S\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4040\"><\/a><\/p>\n<h2>4040<\/h2>\n<p>12-bit asynchronous binary counter with reset.<\/p>\n<pre>    +---+--+---+\r\nQ11 |1  +--+ 16| VCC\r\n Q5 |2       15| Q10\r\n Q4 |3       14| Q9\r\n Q6 |4       13| Q7\r\n Q3 |5  4040 12| Q8\r\n Q2 |6       11| RST\r\n Q1 |7       10| \/CLK\r\nGND |8        9| Q0\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4041\"><\/a><\/p>\n<h2>4041<\/h2>\n<p>Quad buffers with complementary outputs.<\/p>\n<pre>    +---+--+---+             +---*---+---+\r\n 1Y |1  +--+ 14| VCC         | A | Y |\/Y |       Y = A\r\n\/1Y |2       13| 4A          +===*===+===+\r\n 1A |3       12| \/4Y         | 0 | 0 | 1 |\r\n 2Y |4  4041 11| 4Y          | 1 | 1 | 0 |\r\n\/2Y |5       10| 3A          +---*---+---+\r\n 2A |6        9| \/3Y\r\nGND |7        8| 3Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4042\"><\/a><\/p>\n<h2>4042<\/h2>\n<p>4-bit transparent latch with selectable latch enable polarity and complementary outputs.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+---+\r\n Q3 |1  +--+ 16| VCC         | LE| LP| D | Q |\/Q |\r\n Q0 |2       15| \/Q3         +===+===+===*===+===+\r\n\/Q0 |3       14| D3          | 0 | 0 | 0 | 0 | 1 |\r\n D0 |4       13| D2          | 0 | 0 | 1 | 1 | 0 |\r\n LE |5  4042 12| \/Q2         | 1 | 0 | X | - | - |\r\n LP |6       11| Q2          | 1 | 1 | 0 | 0 | 1 |\r\n D2 |7       10| Q1          | 1 | 1 | 1 | 1 | 0 |\r\nGND |8        9| \/Q1         | 0 | 1 | X | - | - |\r\n    +----------+             +---+---+---*---+---+\r\n<\/pre>\n<p><a name=\"4043\"><\/a><\/p>\n<h2>4043<\/h2>\n<p>Quad 3-state S-R latches with overriding set.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n 1Q |1  +--+ 16| VCC         | S | R | OE| Q |\r\n 2Q |2       15| 1R          +===+===+===*===+\r\n 2R |3       14| 1S          | X | X | 0 | Z |\r\n 2S |4       13|             | 0 | 0 | 1 | - |\r\n OE |5  4043 12| 4S          | 0 | 1 | 1 | 1 |\r\n 3S |6       11| 4R          | 1 | 0 | 1 | 0 |\r\n 3R |7       10| 4Q          | 1 | 1 | 1 | 1 |\r\nGND |8        9| 3Q          +---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4044\"><\/a><\/p>\n<h2>4044<\/h2>\n<p>Quad 3-state S-R latches with overriding reset.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n 1Q |1  +--+ 16| VCC         | S | R | OE| Q |\r\n    |2       15| 4S          +===+===+===*===+\r\n 2S |3       14| 4R          | X | X | 0 | Z |\r\n 2R |4       13| 2Q          | 0 | 0 | 1 | - |\r\n OE |5  4044 12| 4R          | 0 | 1 | 1 | 1 |\r\n 3S |6       11| 4S          | 1 | 0 | 1 | 0 |\r\n 3R |7       10| 4Q          | 1 | 1 | 1 | 0 |\r\nGND |8        9| 3Q          +---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4045\"><\/a><\/p>\n<h2>4045<\/h2>\n<p>21-bit asynchronous binary counter with oscillator and reset input.<br \/>\nOnly two 3% duty cycle outputs (180` out of phase) from the last counter stage are available. Can be used to generate a 1Hz clock signal using a 2.097152MHz crystal. P and N MOSFET source connections from the oscillator inverter are brought out of the package to allow the use of source resistors, but usually pS=VCC and nS=GND.<\/p>\n<pre>    +---+--+---+\r\n pS |1  +--+ 16| X1\r\n nS |2       15| X0\r\nVCC |3       14| GND\r\n    |4       13|\r\n    |5  4045 12|\r\n    |6       11|\r\n QA |7       10|\r\n QB |8        9|\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4046\"><\/a><\/p>\n<h2>4046<\/h2>\n<p>Phase Locked Loop.<\/p>\n<pre>       +---+--+---+\r\nPCPout |1  +--+ 16| VCC\r\nPC1out |2       15| Zener\r\n PCinB |3       14| PCinA\r\nVCOout |4       13| PC2out\r\n   \/EN |5  4046 12| R2\r\n   C1A |6       11| R1\r\n   C1B |7       10| SFout\r\n   GND |8        9| VCOin\r\n       +----------+\r\n<\/pre>\n<p><a name=\"4047\"><\/a><\/p>\n<h2>4047<\/h2>\n<p>Low-power astable\/monostable multivibrator with oscillator output.<\/p>\n<pre>      +---+--+---+\r\n Cext |1  +--+ 14| VCC\r\n Rext |2       13| OSC\r\nRCext |3       12| RETRIG\r\n \/AST |4  4047 11| \/Q\r\n  AST |5       10| Q\r\n  \/TR |6        9| RST\r\n  GND |7        8| TR\r\n      +----------+\r\n<\/pre>\n<p><a name=\"4048\"><\/a><\/p>\n<h2>4048<\/h2>\n<p>3-state 8-input multifunction gate.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*------------------------+\r\n  Y |1  +--+ 16| VCC         | S2| S1| S0| OE| Output function        |\r\n OE |2       15| X           +===+===+===+===*========================+\r\n  A |3       14| H           | X | X | X | 0 | Z                      |\r\n  B |4       13| G           | 0 | 0 | 0 | 1 | 8-input NOR            |\r\n  C |5  4048 12| F           | 0 | 0 | 1 | 1 | 8-input OR             |\r\n  D |6       11| E           | 0 | 1 | 0 | 1 | 2-wide 4-input OR-AND  |\r\n S1 |7       10| S2          | 0 | 1 | 1 | 1 | 2-wide 4-input OR-NAND |\r\nGND |8        9| S0          | 1 | 0 | 0 | 1 | 8-input AND            |\r\n    +----------+             | 1 | 0 | 1 | 1 | 8-input NAND           |\r\n                             | 1 | 1 | 0 | 1 | 2-wide 4-input AND-NOR |\r\n                             | 1 | 1 | 1 | 1 | 2-wide 4-input AND-OR  |\r\n                             +---+---+---+---*------------------------+\r\n<\/pre>\n<p><a name=\"4049\"><\/a><\/p>\n<h2>4049<\/h2>\n<p>Hex inverters with high-to-low level shifter inputs.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\nVCC |1  +--+ 16|             | A |\/Y |          \/Y = A\r\n\/Y1 |2       15| \/Y6         +===*===+\r\n A1 |3       14| A6          | 0 | 1 |\r\n\/Y2 |4       13|             | 1 | 0 |\r\n A2 |5  4049 12| \/Y5         +---*---+\r\n\/Y3 |6       11| A5\r\n A3 |7       10| \/Y4\r\nGND |8        9| A4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4066\"><\/a><\/p>\n<h2>4066<\/h2>\n<p>Quad analog switches.<\/p>\n<pre>     +---+--+---+\r\n  1X |1  +--+ 14| VCC\r\n  1Y |2       13| 1EN\r\n  2Y |3       12| 4EN\r\n  2X |4  4016 11| 4X\r\n 2EN |5  4066 10| 4Y\r\n 3EN |6        9| 3Y\r\n GND |7        8| 3X\r\n     +----------+<\/pre>\n<h2>4016<\/h2>\n<p>Quad analog switches.<\/p>\n<pre>     +---+--+---+\r\n  1X |1  +--+ 14| VCC\r\n  1Y |2       13| 1EN\r\n  2Y |3       12| 4EN\r\n  2X |4  4016 11| 4X\r\n 2EN |5  4066 10| 4Y\r\n 3EN |6        9| 3Y\r\n GND |7        8| 3X\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4050\"><\/a><\/p>\n<h2>4050<\/h2>\n<p>Hex buffers with high-to-low level shifter inputs.<\/p>\n<pre>    +---+--+---+             +---*---+\r\nVCC |1  +--+ 16|             | A | Y |           Y = A\r\n Y1 |2       15| Y6          +===*===+\r\n A1 |3       14| A6          | 0 | 0 |\r\n Y2 |4       13|             | 1 | 1 |\r\n A2 |5  4050 12| Y5          +---*---+\r\n Y3 |6       11| A5\r\n A3 |7       10| Y4\r\nGND |8        9| A4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4051\"><\/a><\/p>\n<h2>4051<\/h2>\n<p>8-to-1 line analog multiplexer\/demultiplexer with dual power supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+--+---+\r\n X4 |1  +--+ 16| VCC\r\n X6 |2       15| X2\r\n  Y |3       14| X1\r\n X7 |4       13| X0\r\n X5 |5  4051 12| X3\r\n\/EN |6       11| S0\r\nVEE |7       10| S1\r\nGND |8        9| S2\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4052\"><\/a><\/p>\n<h2>4052<\/h2>\n<p>8-to-2 line analog multiplexer\/demultiplexer with dual power supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+--+---+\r\n1X0 |1  +--+ 16| VCC\r\n1X2 |2       15| 2X2\r\n 1Y |3       14| 2X1\r\n1X3 |4       13| 2Y\r\n1X1 |5  4052 12| 2X0\r\n\/EN |6       11| 2X3\r\nVEE |7       10| S0\r\nGND |8        9| S1\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4053\"><\/a><\/p>\n<h2>4053<\/h2>\n<p>Triple 2-to-1 line analog multiplexer\/demultiplexer with dual power supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+--+---+\r\n1X0 |1  +--+ 16| VCC\r\n1X1 |2       15| 1Y\r\n2X1 |3       14| 3Y\r\n 2Y |4       13| 3X1\r\n2X0 |5  4053 12| 3X0\r\n\/EN |6       11| 3S\r\nVEE |7       10| 1S\r\nGND |8        9| 2S\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4054\"><\/a><\/p>\n<h2>4054<\/h2>\n<p>Quad level shifters\/LCD drivers with input latches.<br \/>\nA level-shifted inverse of the P (phase) input should be connected to the backplane of the LCD; this can be done by using one section of the 4054 with A=0 and LE=1.<\/p>\n<pre>    +---+--+---+             +---+---*---+            _\r\n1LE |1  +--+ 16| VCC         | LE| A | R |       Y = R$P\r\n  P |2       15| 1A          +===+===*===+\r\n 1Y |3       14| 2LE         | 0 | X | - |\r\n 2Y |4       13| 2A          | 1 | 0 | 0 |\r\n 3Y |5  4054 12| 3LE         | 1 | 1 | 1 |\r\n 4Y |6       11| 3A          +---+---*---+\r\nVEE |7       10| 4LE\r\nGND |8        9| 4A\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4055\"><\/a><\/p>\n<h2>4055<\/h2>\n<p>BCD to 7-segment decoder\/LCD driver.<br \/>\nThe Po (phase) output should be connected to the backplane of the LCD.<\/p>\n<pre>    +---+--+---+\r\n Po |1  +--+ 16| VCC\r\n A2 |2       15| YF\r\n A1 |3       14| YG\r\n A3 |4       13| YE\r\n A0 |5  4055 12| YD\r\n Pi |6       11| YC\r\nVEE |7       10| YB\r\nGND |8        9| YA\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4056\"><\/a><\/p>\n<h2>4056<\/h2>\n<p>BCD to 7-segment decoder\/LCD driver with input latches.<br \/>\nA level-shifted inverse of the P (phase) input should be connected to the backplane of the LCD.<\/p>\n<pre>    +---+--+---+\r\n LE |1  +--+ 16| VCC\r\n A2 |2       15| YF\r\n A1 |3       14| YG\r\n A3 |4       13| YE\r\n A0 |5  4056 12| YD\r\n  P |6       11| YC\r\nVEE |7       10| YB\r\nGND |8        9| YA\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4059\"><\/a><\/p>\n<h2>4059<\/h2>\n<p>Divide by N counter.<br \/>\nKa, Kb, Kc are the modulus (divide by number) of the 1st and last counting sections. N can range from 3 to 15999. The down-counter is preset by 15 jam inputs.<\/p>\n<pre>    +-----+--+-----+\r\nCLK |1    +--+   24| VCC\r\n LD |2           23| Q\r\n J1 |3           22| J5\r\n J2 |4           21| J6\r\n J3 |5           20| J7\r\n J4 |6           19| J8\r\nJ16 |7    4059   18| J9\r\nJ15 |8           17| J10\r\nJ14 |9           16| J11\r\nJ13 |10          15| J12\r\n Kc |11          14| Ka\r\nGND |12          13| Kb\r\n    +--------------+\r\n<\/pre>\n<p><a name=\"4060\"><\/a><\/p>\n<h2>4060<\/h2>\n<p>14-bit asynchronous binary counter with oscillator and reset input.<br \/>\nQ0,Q1,Q2 and Q10 outputs are missing.<\/p>\n<pre>    +---+--+---+\r\nQ11 |1  +--+ 16| VCC\r\nQ12 |2       15| Q9\r\nQ13 |3       14| Q7\r\n Q5 |4       13| Q8\r\n Q4 |5  4060 12| RST\r\n Q6 |6       11| X1\r\n Q3 |7       10| X0\r\nGND |8        9| X2\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4063\"><\/a><\/p>\n<h2>4063<\/h2>\n<p>4-bit noninverting magnitude comparator with cascade inputs.<\/p>\n<pre>     +---+--+---+\r\n  B3 |1  +--+ 16| VCC\r\nIA&lt;B |2       15| A3\r\nIA=B |3       14| B2\r\nIA&gt;B |4       13| A2\r\nOA&gt;B |5  4063 12| A1\r\nOA=B |6       11| B1\r\nOA&lt;B |7       10| A0\r\n GND |8        9| B0\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4066\"><\/a><\/p>\n<h2>4066<\/h2>\n<p>Quad analog switches.<\/p>\n<pre>     +---+--+---+\r\n  1X |1  +--+ 14| VCC\r\n  1Y |2       13| 1EN\r\n  2Y |3       12| 4EN\r\n  2X |4  4016 11| 4X\r\n 2EN |5  4066 10| 4Y\r\n 3EN |6        9| 3Y\r\n GND |7        8| 3X\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4067\"><\/a><\/p>\n<h2>4067<\/h2>\n<p>16-to-1 line analog multiplexer\/demultiplexer.<\/p>\n<pre>    +-----+--+-----+\r\n  Y |1    +--+   24| VCC\r\n X7 |2           23| X8\r\n X6 |3           22| X9\r\n X5 |4           21| X10\r\n X4 |5           20| X11\r\n X3 |6           19| X12\r\n X2 |7    4067   18| X13\r\n X1 |8           17| X14\r\n X0 |9           16| X15\r\n S0 |10          15| \/EN\r\n S1 |11          14| S2\r\nGND |12          13| S3\r\n    +--------------+\r\n<\/pre>\n<p><a name=\"4068\"><\/a><\/p>\n<h2>4068<\/h2>\n<p>8-input AND\/NAND gate with complementary outputs.<\/p>\n<pre>    +---+--+---+\r\n  Y |1  +--+ 14| VCC         Y = ABCDEFGH\r\n  A |2       13| \/Y\r\n  B |3       12| H\r\n  C |4  4068 11| G\r\n  D |5       10| F\r\n    |6        9| E\r\nGND |7        8|\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4069\"><\/a><\/p>\n<h2>4069<\/h2>\n<p>Hex inverters.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\n 1A |1  +--+ 14| VCC         | A |\/Y |          \/Y = A\r\n\/1Y |2       13| 6A          +===*===+\r\n 2A |3       12| \/6Y         | 0 | 1 |\r\n\/2Y |4  4069 11| 5A          | 1 | 0 |\r\n 3A |5       10| \/5Y         +---*---+\r\n\/3Y |6        9| 4A\r\nGND |7        8| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4070\"><\/a><\/p>\n<h2>4070<\/h2>\n<p>Quad 2-input XOR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+                    _   _\r\n 1A |1  +--+ 14| VCC         | A | B | Y |       Y = A$B = (A.B)+(A.B)\r\n 1B |2       13| 4B          +===+===*===+\r\n 1Y |3       12| 4A          | 0 | 0 | 0 |\r\n 2Y |4  4070 11| 4Y          | 0 | 1 | 1 |\r\n 2A |5       10| 3Y          | 1 | 0 | 1 |\r\n 2B |6        9| 3B          | 1 | 1 | 0 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4071\"><\/a><\/p>\n<h2>4071<\/h2>\n<p>Quad 2-input OR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | Y |       Y = A+B\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3       12| 4A          | 0 | 0 | 0 |\r\n\/2Y |4  4071 11| \/4Y         | 0 | 1 | 1 |\r\n 2A |5       10| \/3Y         | 1 | 0 | 1 |\r\n 2B |6        9| 3B          | 1 | 1 | 1 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4072\"><\/a><\/p>\n<h2>4072<\/h2>\n<p>Dual 4-input OR gates.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+\r\n 1Y |1  +--+ 14| VCC         | A | B | C | D |\/Y |   Y = A+B+C+D\r\n 1A |2       13| 2Y          +===+===+===+===*===+\r\n 1B |3       12| 2D          | 0 | 0 | 0 | 0 | 0 |\r\n 1C |4  4072 11| 2C          | 0 | 0 | 0 | 1 | 1 |\r\n 1D |5       10| 2B          | 0 | 0 | 1 | X | 1 |\r\n    |6        9| 2A          | 0 | 1 | X | X | 1 |\r\nGND |7        8|             | 1 | X | X | X | 1 |\r\n    +----------+             +---+---+---+---*---+\r\n<\/pre>\n<p><a name=\"4073\"><\/a><\/p>\n<h2>4073<\/h2>\n<p>Triple 3-input AND gates.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | C | Y |   Y = ABC\r\n 1B |2       13| 3A          +===+===+===*===+\r\n 2A |3       12| 3B          | 0 | X | X | 0 |\r\n 2B |4  4073 11| 3C          | 1 | 0 | X | 0 |\r\n 2C |5       10| 3Y          | 1 | 1 | 0 | 0 |\r\n 2Y |6        9| 1Y          | 1 | 1 | 1 | 1 |\r\nGND |7        8| 1C          +---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4075\"><\/a><\/p>\n<h2>4075<\/h2>\n<p>Triple 3-input OR gates.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | C | Y |   Y = A+B+C\r\n 1B |2       13| 3A          +===+===+===*===+\r\n 2A |3       12| 3B          | 0 | 0 | 0 | 0 |\r\n 2B |4  4075 11| 3C          | 0 | 0 | 1 | 1 |\r\n 2C |5       10| 3Y          | 0 | 1 | X | 1 |\r\n 2Y |6        9| 1Y          | 1 | X | X | 1 |\r\nGND |7        8| 1C          +---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4076\"><\/a><\/p>\n<h2>4076<\/h2>\n<p>4-bit 3-state D flip-flop with reset, dual clock enables and dual output enables.<\/p>\n<pre>     +---+--+---+\r\n\/OE1 |1  +--+ 16| VCC\r\n\/OE2 |2       15| RST\r\n  Q0 |3       14| D0\r\n  Q1 |4       13| D1\r\n  Q2 |5  4076 12| D2\r\n  Q3 |6       11| D3\r\n CLK |7       10| \/CLKEN1\r\n GND |8        9| \/CLKEN2\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4077\"><\/a><\/p>\n<h2>4077<\/h2>\n<p>Quad 2-input XNOR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+            _     _ _\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |       Y = A$B = (A.B)+(A.B)\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3       12| 4A          | 0 | 0 | 1 |\r\n\/2Y |4  4077 11| \/4Y         | 0 | 1 | 0 |\r\n 2A |5       10| \/3Y         | 1 | 0 | 0 |\r\n 2B |6        9| 3B          | 1 | 1 | 1 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4078\"><\/a><\/p>\n<h2>4078<\/h2>\n<p>8-input OR\/NOR gate with complementary outputs.<\/p>\n<pre>    +---+--+---+\r\n  Y |1  +--+ 14| VCC         Y=A+B+C+D+E+F+G+H\r\n  A |2       13| \/Y\r\n  B |3       12| H\r\n  C |4  4078 11| G\r\n  D |5       10| F\r\n    |6        9| E\r\nGND |7        8|\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4081\"><\/a><\/p>\n<h2>4081<\/h2>\n<p>Quad 2-input AND gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | Y |       Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n 1Y |3       12| 4A          | 0 | 0 | 0 |\r\n 2Y |4  4081 11| 4Y          | 0 | 1 | 0 |\r\n 2A |5       10| 3Y          | 1 | 0 | 0 |\r\n 2B |6        9| 3B          | 1 | 1 | 1 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4082\"><\/a><\/p>\n<h2>4082<\/h2>\n<p>Dual 4-input AND gates.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+\r\n 1Y |1  +--+ 14| VCC         | A | B | C | D | Y |    Y = ABCD\r\n 1A |2       13| 2Y          +===+===+===+===*===+\r\n 1B |3       12| 2D          | 0 | X | X | X | 0 |\r\n 1C |4  4082 11| 2C          | 1 | 0 | X | X | 0 |\r\n 1D |5       10| 2B          | 1 | 1 | 0 | X | 0 |\r\n    |6        9| 2A          | 1 | 1 | 1 | 0 | 0 |\r\nGND |7        8|             | 1 | 1 | 1 | 1 | 1 |\r\n    +----------+             +---+---+---+---*---+\r\n<\/pre>\n<p><a name=\"4085\"><\/a><\/p>\n<h2>4085<\/h2>\n<p>Dual 3-wide 2\/1-input AND-NOR gates.<\/p>\n<pre>    +---+--+---+                 _______\r\n 1A |1  +--+ 14| VCC        \/Y = AB+CD+E\r\n 1B |2       13| 1D\r\n\/1Y |3       12| 1C\r\n\/2Y |4  4085 11| 1E\r\n 2A |5       10| 2E\r\n 2B |6        9| 2D\r\nGND |7        8| 2C\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4086\"><\/a><\/p>\n<h2>4086<\/h2>\n<p>6-wide 2\/1-input AND-NOR gate.<\/p>\n<pre>    +---+--+---+                 ________________\r\n  A |1  +--+ 14| VCC        \/Y = AB+CD+EF+GH+J+\/K\r\n  B |2       13| H\r\n \/Y |3       12| G\r\n    |4  4086 11| K\r\n  C |5       10| J\r\n  D |6        9| F\r\nGND |7        8| E\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4089\"><\/a><\/p>\n<h2>4089<\/h2>\n<p>4-bit synchronous binary rate multiplier.<\/p>\n<pre>     +---+--+---+\r\n Q15 |1  +--+ 16| VCC\r\n  D2 |2       15| D1\r\n  D3 |3       14| D0\r\n SET |4       13| RST\r\n  \/Q |5  4089 12| CASC\r\n   Q |6       11| CIN\r\nCOUT |7       10| STB\r\n GND |8        9| CLK\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4093\"><\/a><\/p>\n<h2>4093<\/h2>\n<p>Quad 2-input NAND gates with schmitt-trigger inputs.<br \/>\n0.9V typical input hysteresis at VCC=+5V and 2.3V at VCC=+10V.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3       12| 4A          | 0 | 0 | 1 |\r\n\/2Y |4  4093 11| \/4Y         | 0 | 1 | 1 |\r\n 2A |5       10| \/3Y         | 1 | 0 | 1 |\r\n 2B |6        9| 3B          | 1 | 1 | 0 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4094\"><\/a><\/p>\n<h2>4094<\/h2>\n<p>8-bit 3-state serial-in parallel-out shift register with output latches.<br \/>\nQ7&#8242; is Q7 delayed by half a cycle (i.e. clocked on falling edge).<\/p>\n<pre>    +---+--+---+\r\n LE |1  +--+ 16| VCC\r\n  D |2       15| OE\r\nCLK |3       14| Y4\r\n Y0 |4       13| Y5\r\n Y1 |5  4094 12| Y6\r\n Y2 |6       11| Y7\r\n Y3 |7       10| Q7\r\nGND |8        9| Q7'\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4095\"><\/a><\/p>\n<h2>4095<\/h2>\n<p>J-K flip-flop with triple ANDed J an K inputs, set and reset.<\/p>\n<pre>     +---+--+---+            +--------+--------+---+---+---*---+---+\r\n     |1  +--+ 14| VCC        |J1.J2.J3|K1.K2.K3|CLK|SET|RST| Q |\/Q |\r\n RST |2       13| SET        +========+========+===+===+===*===+===+\r\n  J1 |3       12| CLK        |    X   |    X   | X | 1 | 1 | 0 | 0 |\r\n  J2 |4  4095 11| K3         |    X   |    X   | X | 1 | 0 | 1 | 0 |\r\n  J3 |5       10| K2         |    X   |    X   | X | 0 | 1 | 0 | 1 |\r\n  \/Q |6        9| K1         |    0   |    0   | \/ | 0 | 0 | - | - |\r\n GND |7        8| Q          |    0   |    1   | \/ | 0 | 0 | 0 | 1 |\r\n     +----------+            |    1   |    0   | \/ | 0 | 0 | 1 | 0 |\r\n                             |    1   |    1   | \/ | 0 | 0 |\/Q | Q |\r\n                             |    X   |    X   |!\/ | 0 | 0 | - | - |\r\n                             +--------+--------+---+---+---*---+---+\r\n<\/pre>\n<p><a name=\"4096\"><\/a><\/p>\n<h2>4096<\/h2>\n<p>J-K flip-flop with triple ANDed J an K inputs (one inverted), set and reset.<\/p>\n<pre>     +---+--+---+            +---------+---------+---+---+---*---+---+\r\n     |1  +--+ 14| VCC        |J1.J2.\/J3|K1.K2.\/K3|CLK|SET|RST| Q |\/Q |\r\n RST |2       13| SET        +=========+=========+===+===+===*===+===+\r\n  J1 |3       12| CLK        |    X    |    X    | X | 1 | 1 | 0 | 0 |\r\n  J2 |4  4096 11| K1         |    X    |    X    | X | 1 | 0 | 1 | 0 |\r\n \/J3 |5       10| K2         |    X    |    X    | X | 0 | 1 | 0 | 1 |\r\n  \/Q |6        9| \/K3        |    0    |    0    | \/ | 0 | 0 | - | - |\r\n GND |7        8| Q          |    0    |    1    | \/ | 0 | 0 | 0 | 1 |\r\n     +----------+            |    1    |    0    | \/ | 0 | 0 | 1 | 0 |\r\n                             |    1    |    1    | \/ | 0 | 0 |\/Q | Q |\r\n                             |    X    |    X    |!\/ | 0 | 0 | - | - |\r\n                             +---------+---------+---+---+---*---+---+\r\n<\/pre>\n<p><a name=\"4097\"><\/a><\/p>\n<h2>4097<\/h2>\n<p>16-to-2 line analog multiplexer\/demultiplexer.<\/p>\n<pre>    +-----+--+-----+\r\n 1Y |1    +--+   24| VCC\r\n1X7 |2           23| 2X0\r\n1X6 |3           22| 2X1\r\n1X5 |4           21| 2X2\r\n1X4 |5           20| 2X3\r\n1X3 |6           19| 2X4\r\n1X2 |7    4097   18| 2X5\r\n1X1 |8           17| 2Y\r\n1X0 |9           16| 2X6\r\n S0 |10          15| 2X7\r\n S1 |11          14| S2\r\nGND |12          13| \/EN\r\n    +--------------+\r\n<\/pre>\n<p><a name=\"4098\"><\/a><\/p>\n<h2>4098<\/h2>\n<p>Dual monostable multivibrator, retriggerable, resettable.<\/p>\n<pre>       +---+--+---+\r\n 1Cext |1  +--+ 16| VCC\r\n1RCext |2       15| 2Cext\r\n  1RST |3       14| 2RCext\r\n   1TR |4       13| 2RST\r\n  \/1TR |5  4098 12| 2TR\r\n    1Q |6       11| \/2TR\r\n   \/1Q |7       10| 2Q\r\n   GND |8        9| \/2Q\r\n       +----------+\r\n<\/pre>\n<p><a name=\"4099\"><\/a><\/p>\n<h2>4099<\/h2>\n<p>1-of-8 addressable latch with reset.<\/p>\n<pre>    +---+--+---+\r\n Q7 |1  +--+ 16| VCC\r\nRST |2       15| Q6\r\n  D |3       14| Q5\r\n\/WR |4       13| Q4\r\n A0 |5  4099 12| Q3\r\n A1 |6       11| Q2\r\n A2 |7       10| Q1\r\nGND |8        9| Q0\r\n    +----------+<\/pre>\n<h2>4316<\/h2>\n<p>Quad analog switches with enable input and dual power supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+--+---+\r\n 1X |1  +--+ 16| VCC\r\n 1Y |2       15| 1EN\r\n 2Y |3       14| 4EN\r\n 2X |4       13| 4X2\r\n EN |5  4316 12| 4Y3\r\n EN |6       11| 3Y\r\n EN |7       10| 3X\r\nGND |8        9| VEE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4351\"><\/a><\/p>\n<h2>4351<\/h2>\n<p>8-to-1 line analog multiplexer\/demultiplexer with address latch and dualpower supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+--+---+\r\n1X0 |1  +--+ 18| VCC\r\n1X1 |2       17| X2\r\n2X1 |3       16| X1\r\n 2Y |4       15| X0\r\n2X0 |5  4351 14| X3\r\n\/EN |6       13| S0\r\n EN |7       12| S1\r\nVEE |8       11| S2\r\nGND |9       10| LE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4352\"><\/a><\/p>\n<h2>4352<\/h2>\n<p>8-to-2 line analog multiplexer\/demultiplexer with address latch and dualpower supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+  +---+\r\n1X0 |1  +--+ 18| VCC\r\n1X2 |2       17| 2X2\r\n 1Y |3       16| 2X1\r\n1X3 |4       15| 2Y\r\n1X1 |5  4352 14| 2X0\r\n\/EN |6       13| 2X3\r\n EN |7       12| S0\r\nVEE |8       11| S1\r\nGND |9       10| LE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4353\"><\/a><\/p>\n<h2>4353<\/h2>\n<p>Triple 2-to-1 line analog multiplexer\/demultiplexer with address latch anddual power supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+  +---+\r\n1X0 |1  +--+ 18| VCC\r\n1X1 |2       17| 1Y\r\n2X1 |3       16| 3Y\r\n 2Y |4       15| 3X1\r\n2X0 |5  4353 14| 3X0\r\n\/EN |6       13| 3S\r\n EN |7       12| 1S\r\nVEE |8       11| 2S\r\nGND |9       10| LE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4500\"><\/a><\/p>\n<h2>4500<\/h2>\n<p>Industrial Control Unit.<br \/>\nIf you _really_ want to use this RRRRISC, try to get the &#8216;MC14500B IndustrialControl Unit Handbook&#8217; from Motorola (sorry, no ISBN number).<\/p>\n<pre>    +---+  +---+\r\nRST |1  +--+ 16| VCC\r\n WR |2       15| RR\r\n  D |3       14| X0\r\n I3 |4       13| X1\r\n I2 |5  4500 12| JMP\r\n I1 |6       11| RTN\r\n I0 |7       10| FLG0\r\nGND |8        9| FLGF\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4502\"><\/a><\/p>\n<h2>4502<\/h2>\n<p>6-bit 3-state inverting buffer\/line driver with NOR inputs.<\/p>\n<pre>    +---+  +---+             +---+---+---+---+\r\n A0 |1  +--+ 16| VCC         |\/OE| A | B I\/Y |\r\n\/Y0 |2       15| A5          +===+===+===+===+\r\n A1 |3       14| \/Y5         | 1 | X | X I Z |\r\n\/OE |4       13| A4          | 0 | 0 | 0 I 1 |\r\n\/Y1 |5  4502 12| B           | 0 | 1 | 0 I 0 |\r\n A2 |6       11| \/Y4         | 0 | X | 1 I 0 |\r\n\/Y2 |7       10| A3          +---+---+---+---+\r\nGND |8        9| \/Y3\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4503\"><\/a><\/p>\n<h2>4503<\/h2>\n<p>2\/4-bit 3-state noninverting buffer\/line driver.<\/p>\n<pre>     +---+  +---+            +---+---+---+\r\n\/1OE |1  +--+ 16| VCC        |\/OE| A I Y |\r\n 1A1 |2       15| \/2OE       +===+===+===+\r\n 1Y1 |3       14| 2A2        | 1 | X I Z |\r\n 1A2 |4       13| 2Y2        | 0 | 0 I 0 |\r\n 1Y2 |5  4503 12| 2A1        | 0 | 1 I 1 |\r\n 1A3 |6       11| 2Y1        +---+---+---+\r\n 1Y3 |7       10| 1A4\r\n GND |8        9| 1Y4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4508\"><\/a><\/p>\n<h2>4508<\/h2>\n<p>Dual 4-bit 3-state transparent latch with reset.<\/p>\n<pre>     +-----+  +-----+        +---+---+---+---+\r\n1RST |1    +--+   24| VCC    |\/OE| LE| D I Q |\r\n 1LE |2           23| 2Q3    +===+===+===+===+\r\n\/1OE |3           22| 2D3    | 1 | X | X I Z |\r\n 1D0 |4           21| 2Q2    | 0 | 0 | X I - |\r\n 1Q0 |5           20| 2D2    | 0 | 1 | 0 I 0 |\r\n 1D1 |6           19| 2Q1    | 0 | 1 | 1 I 1 |\r\n 1Q1 |7    4508   18| 2D1    +---+---+---+---+\r\n 1D2 |8           17| 2Q0\r\n 1Q2 |9           16| 2D0\r\n 1D3 |10          15| \/2OE\r\n 1Q3 |11          14| 2LE\r\n GND |12          13| 2RST\r\n     +--------------+\r\n<\/pre>\n<p><a name=\"4510\"><\/a><\/p>\n<h2>4510<\/h2>\n<p>4-bit synchronous decade up\/down counter with asynchronous load, reset andripple carry output.<\/p>\n<pre>     +---+  +---+\r\n  LD |1  +--+ 16| VCC\r\n  Q3 |2       15| CLK\r\n  P3 |3       14| Q2\r\n  P0 |4       13| P2\r\n\/RCI |5  4510 12| P1\r\n  Q0 |6       11| Q1\r\n\/RCO |7       10| UP\/\/DN\r\n GND |8        9| RST\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4512\"><\/a><\/p>\n<h2>4512<\/h2>\n<p>8-to-1 line 3-state data selector\/multiplexer with AND inputs.<\/p>\n<pre>    +---+  +---+\r\n A0 |1  +--+ 16| VCC         Y = An.\/B\r\n A1 |2       15| \/OE\r\n A2 |3       14| Y\r\n A3 |4       13| S2\r\n A4 |5  4512 12| S1\r\n A5 |6       11| S0\r\n A6 |7       10| \/B\r\nGND |8        9| A7\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4514\"><\/a><\/p>\n<h2>4514<\/h2>\n<p>1-of-16 noninverting decoder\/demultiplexer with address latches.<\/p>\n<pre>    +---+  +---+\r\n LE |1  +--+ 24| VCC\r\n S0 |2       23| \/EN\r\n S1 |3       22| S3\r\n Y7 |4       21| S2\r\n Y6 |5       20| Y10\r\n Y5 |6       19| Y11\r\n Y4 |7  4514 18| Y8\r\n Y3 |8       17| Y9\r\n Y2 |9       16| Y15\r\n Y1 |10      15| Y14\r\n Y0 |11      14| Y13\r\nGND |12      13| Y12\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4516\"><\/a><\/p>\n<h2>4516<\/h2>\n<p>4-bit synchronous binary up\/down counter with asynchronous load, reset andripple carry output.<\/p>\n<pre>     +---+  +---+\r\n  LD |1  +--+ 16| VCC\r\n  Q3 |2       15| CLK\r\n  P3 |3       14| Q2\r\n  P0 |4       13| P2\r\n\/RCI |5  4516 12| P1\r\n  Q0 |6       11| Q1\r\n\/RCO |7       10| UP\/\/DN\r\n GND |8        9| RST\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4518\"><\/a><\/p>\n<h2>4518<\/h2>\n<p>Dual 4-bit asynchronous decade counters with reset and both active high andactive low clocks.<\/p>\n<pre>      +---+  +---+\r\n 1CLK |1  +--+ 16| VCC\r\n\/1CLK |2       15| 2RST\r\n  1Q0 |3       14| 2Q3\r\n  1Q1 |4       13| 2Q2\r\n  1Q2 |5  4518 12| 2Q1\r\n  1Q3 |6       11| 2Q0\r\n 1RST |7       10| \/2CLK\r\n  GND |8        9| 2CLK\r\n      +----------+\r\n<\/pre>\n<p><a name=\"4521\"><\/a><\/p>\n<h2>4521<\/h2>\n<p>24-bit asynchronous binary counter with oscillator and res For the buffer to be used, GND&#8217; et input,and one CMOS buffer with separate power supply.<br \/>\nQ0&#8230;Q17 outputs are missing. and VCC&#8217;must be connected to GND and VCC (optionally using series resistors).<\/p>\n<pre>     +---+  +---+            +---+---+\r\n Q24 |1  +--+ 16| VCC        | A I Y |\r\n RST |2       15| Q23        +===+===+\r\nGND' |3       14| Q22        | 0 I 0 |\r\n   Y |4       13| Q21        | 1 I 1 |\r\nVCC' |5  4521 12| Q20        +---+---+\r\n   A |6       11| Q19\r\n  X0 |7       10| Q18\r\n GND |8        9| X1\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4527\"><\/a><\/p>\n<h2>4527<\/h2>\n<p>4-bit synchronous decade rate multiplier.<\/p>\n<pre>     +---+  +---+\r\n  Q9 |1  +--+ 16| VCC\r\n  D2 |2       15| D1\r\n  D3 |3       14| D0\r\nSET9 |4       13| RST\r\n  \/Q |5  4527 12| CASC\r\n   Q |6       11| CIN\r\nCOUT |7       10| STB\r\n GND |8        9| CLK\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4532\"><\/a><\/p>\n<h2>4532<\/h2>\n<p>8-to-3 line noninverting priority encoder with cascade inputs.<\/p>\n<pre>    +---+  +---+\r\n A4 |1  +--+ 16| VCC\r\n A5 |2       15| EO\r\n A6 |3       14| GS\r\n A7 |4       13| A3\r\n EI |5  4532 12| A2\r\n Y2 |6       11| A1\r\n Y1 |7       10| A0\r\nGND |8        9| Y0\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4536\"><\/a><\/p>\n<h2>4536<\/h2>\n<p>24-bit programmable frequency divider\/digital timer with oscillator,set and reset inputs. Digitally programmable from 2^1 to 2^24.<br \/>\nConnect MONO via a &gt;10k resistor to ground for square wave output,or to a RC network (R to VCC) for a controlled output pulse width.Maximum guaranteed clock frequency is a pitiful 500kHz.<\/p>\n<pre>        +---+  +---+\r\n    SET |1  +--+ 16| VCC\r\n    RST |2       15| MONO\r\n     X1 |3       14| \/XEN\r\n     X0 |4       13| Q\r\n     X2 |5  4536 12| S3\r\n\/DIV256 |6       11| S2\r\n  CLKEN |7       10| S1\r\n    GND |8        9| S0\r\n        +----------+\r\n<\/pre>\n<p><a name=\"4538\"><\/a><\/p>\n<h2>4538<\/h2>\n<p>Dual precision monostable multivibrator with Schmitt-trigger inputs.<br \/>\nRetriggerable, resettable.For 74HC4538 the Cext pins may be grounded.<\/p>\n<pre>       +---+  +---+\r\n 1Cext |1  +--+ 16| VCC\r\n1RCext |2       15| 2Cext\r\n  1RST |3       14| 2RCext\r\n   1TR |4       13| 2RST\r\n  \/1TR |5  4538 12| 2TR\r\n    1Q |6       11| \/2TR\r\n   \/1Q |7       10| 2Q\r\n   GND |8        9| \/2Q\r\n       +----------+\r\n<\/pre>\n<p><a name=\"4543\"><\/a><\/p>\n<h2>4543<\/h2>\n<p>BCD to 7-segment decoder\/LCD driver with input latch.<br \/>\nThe P (phase) input should be connected to the backplane of the LCD.<\/p>\n<pre>    +---+  +---+\r\n LE |1  +--+ 16| VCC\r\n A2 |2       15| YF\r\n A1 |3       14| YG\r\n A3 |4       13| YE\r\n A0 |5  4543 12| YD\r\n  @ |6       11| YC\r\n BI |7       10| YB\r\nGND |8        9| YA\r\n    +----------+\r\n<\/pre>\n<p><a name=\"4555\"><\/a><\/p>\n<h2>4555<\/h2>\n<p>Dual 1-of-4 noninverting decoder\/demultiplexer.<\/p>\n<pre>     +---+  +---+            +---+---+---+---+---+---+---+\r\n\/1EN |1  +--+ 16| VCC        |\/EN| S1| S0I Y0| Y1| Y2| Y3|\r\n 1S0 |2       15| \/2EN       +===+===+===+===+===+===+===+\r\n 1S1 |3       14| 2S0        | 1 | X | X I 0 | 0 | 0 | 0 |\r\n 1Y0 |4       13| 2S1        | 0 | 0 | 0 I 1 | 0 | 0 | 0 |\r\n 1Y1 |5  4555 12| 2Y0        | 0 | 0 | 1 I 0 | 1 | 0 | 0 |\r\n 1Y2 |6       11| 2Y1        | 0 | 1 | 0 I 0 | 0 | 1 | 0 |\r\n 1Y3 |7       10| 2Y2        | 0 | 1 | 1 I 0 | 0 | 0 | 1 |\r\n GND |8        9| 2Y3        +---+---+---+---+---+---+---+\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4556\"><\/a><\/p>\n<h2>4556<\/h2>\n<p>Dual 1-of-4 inverting decoder\/demultiplexer.<\/p>\n<pre>     +---+  +---+            +---+---+---+---+---+---+---+\r\n\/1EN |1  +--+ 16| VCC        |\/EN| S1| S0I\/Y0|\/Y1|\/Y2|\/Y3|\r\n 1S0 |2       15| \/2EN       +===+===+===+===+===+===+===+\r\n 1S1 |3       14| 2S0        | 1 | X | X I 1 | 1 | 1 | 1 |\r\n\/1Y0 |4       13| 2S1        | 0 | 0 | 0 I 0 | 1 | 1 | 1 |\r\n\/1Y1 |5  4556 12| \/2Y0       | 0 | 0 | 1 I 1 | 0 | 1 | 1 |\r\n\/1Y2 |6       11| \/2Y1       | 0 | 1 | 0 I 1 | 1 | 0 | 1 |\r\n\/1Y3 |7       10| \/2Y2       | 0 | 1 | 1 I 1 | 1 | 1 | 0 |\r\n GND |8        9| \/2Y3       +---+---+---+---+---+---+---+\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4580\"><\/a><\/p>\n<h2>4580<\/h2>\n<p>4&#215;4-bit 3-state synchronous triple-port register file.<\/p>\n<pre>     +-----+--+-----+\r\n 1Q3 |1    +--+   24| VCC\r\n 1Q2 |2           23| 1Q1\r\n 1RD |3           22| 1Q0\r\n 2Q0 |4           21| 2RD\r\n 2Q1 |5           20| D0\r\n 2Q2 |6           19| D1\r\n 2Q3 |7   40108   18| D2\r\n WA0 |8           17| D3\r\n WA1 |9           16| WCLK\r\n2RA1 |10          15| WR\r\n2RA0 |11          14| 1RA1\r\n GND |12          13| 1RA0\r\n     +--------------+\r\n<\/pre>\n<p><a name=\"4585\"><\/a><\/p>\n<h2>4585<\/h2>\n<p>4-bit noninverting magnitude comparator with cascade inputs.<\/p>\n<pre>     +---+  +---+\r\n  B2 |1  +--+ 16| VCC\r\n  A2 |2       15| A3\r\nOA=B |3       14| B3\r\nIA&gt;B |4       13| OA&gt;B\r\nIA&lt;B |5  4585 12| OA&lt;B\r\nIA=B |6       11| B0\r\n  A1 |7       10| A0\r\n GND |8        9| B1\r\n     +----------+\r\n<\/pre>\n<p><a name=\"4599\"><\/a><\/p>\n<h2>4599<\/h2>\n<p>1-of-8 addressable latch with readback and reset.<\/p>\n<pre>    +---+  +---+\r\n Q7 |1  +--+ 18| VCC\r\nRST |2       17| Q6\r\n  D |3       16| Q5\r\n\/WR |4       15| Q4\r\n A0 |5  4599 14| Q3\r\n A1 |6       13| Q2\r\n A2 |7       12| Q1\r\n CE |8       11| Q0\r\nGND |9       10| \/RD\r\n    +----------+\r\n<\/pre>\n<p><a name=\"14500\"><\/a><\/p>\n<h2>14500<\/h2>\n<p>Industrial Control Unit.<br \/>\nIf you _really_ want to use this RRRRISC, try to get the &#8216;MC14500B IndustrialControl Unit Handbook&#8217; from Motorola (sorry, no ISBN number).<\/p>\n<pre>    +---+--+---+\r\nRST |1  +--+ 16| VCC\r\n WR |2       15| RR\r\n  D |3       14| X0\r\n I3 |4       13| X1\r\n I2 |5  4500 12| JMP\r\n I1 |6       11| RTN\r\n I0 |7       10| FLG0\r\nGND |8        9| FLGF\r\n        +----------+\r\n<\/pre>\n<p><a name=\"40108\"><\/a><\/p>\n<h2>40108<\/h2>\n<p>4&#215;4-bit 3-state synchronous triple-port register file.<\/p>\n<pre>     +-----+--+-----+\r\n 1Q3 |1    +--+   24| VCC\r\n 1Q2 |2           23| 1Q1\r\n 1RD |3           22| 1Q0\r\n 2Q0 |4           21| 2RD\r\n 2Q1 |5           20| D0\r\n 2Q2 |6           19| D1\r\n 2Q3 |7   40108   18| D2\r\n WA0 |8           17| D3\r\n WA1 |9           16| WCLK\r\n2RA1 |10          15| WR\r\n2RA0 |11          14| 1RA1\r\n GND |12          13| 1RA0\r\n     +--------------+\r\n<\/pre>\n<p><a name=\"40208\"><\/a><\/p>\n<h2>40208<\/h2>\n<p>4&#215;4-bit 3-state synchronous triple-port register file.<\/p>\n<pre>     +-----+--+-----+\r\n 1Q3 |1    +--+   24| VCC\r\n 1Q2 |2           23| 1Q1\r\n 1RD |3           22| 1Q0\r\n 2Q0 |4           21| 2RD\r\n 2Q1 |5           20| D0\r\n 2Q2 |6           19| D1\r\n 2Q3 |7   40108   18| D2\r\n WA0 |8           17| D3\r\n WA1 |9           16| WCLK\r\n2RA1 |10          15| WR\r\n2RA0 |11          14| 1RA1\r\n GND |12          13| 1RA0\r\n     +--------------+<\/pre>\n<h2>4580<\/h2>\n<p>4&#215;4-bit 3-state synchronous triple-port register file.<\/p>\n<pre>      +-----+--+-----+\r\n  1Q3 |1    +--+   24| VCC\r\n  1Q2 |2           23| 1Q1\r\n  1RD |3           22| 1Q0\r\n  2Q0 |4           21| 2RD\r\n  2Q1 |5           20| D0\r\n  2Q2 |6           19| D1\r\n  2Q3 |7   40108   18| D2\r\n  WA0 |8           17| D3\r\n  WA1 |9           16| WCLK\r\n 2RA1 |10          15| WR\r\n 2RA0 |11          14| 1RA1\r\n  GND |12          13| 1RA0\r\n      +--------------+\r\n<\/pre>\n<p><a name=\"40100\"><\/a><\/p>\n<h2>40100<\/h2>\n<p>32-bit bidirectional serial-in serial-out shift register with two AND gated clocks.<br \/>\nWith \/LOOP input low, data is rotated and serial data input ignored.<\/p>\n<pre>      +---+--+---+\r\n      |1  +--+ 16| VCC\r\n\/CLK2 |2       15|\r\n CLK1 |3       14|\r\n   Q0 |4       13| L\/\/R\r\n      |5 40100 12| Q31\r\n    L |6       11| D\r\n      |7       10|\r\n  GND |8        9| \/LOOP\r\n      +----------+\r\n<\/pre>\n<p><a name=\"40101\"><\/a><\/p>\n<h2>40101<\/h2>\n<p>9-bit odd\/even parity generator\/checker.<\/p>\n<pre>    +---+--+---+\r\n A0 |1  +--+ 14| VCC\r\n A1 |2       13| A8\r\n A2 |3       12| A7\r\n A3 |4 40101 11| A6\r\n A4 |5       10| A5\r\nODD |6        9| EVEN\r\nGND |7        8| \/EN\r\n    +----------+\r\n<\/pre>\n<p><a name=\"40102\"><\/a><\/p>\n<h2>40102<\/h2>\n<p>8-bit (2-digit) synchronous decade down counter with synchronous and asynchronous load and reset. Counter outputs only internally connected but ripple carry and zero detect outputs available.<\/p>\n<pre>       +---+--+---+\r\n   CLK |1  +--+ 16| VCC\r\n  \/RST |2       15| \/SLD\r\n\/CLKEN |3       14| \/RCO\r\n    P0 |4       13| P7\r\n    P1 |5 40102 12| P6\r\n    P2 |6       11| P5\r\n    P3 |7       10| P4\r\n   GND |8        9| \/ALD\r\n       +----------+\r\n<\/pre>\n<p><a name=\"40103\"><\/a><\/p>\n<h2>40103<\/h2>\n<p>8-bit synchronous binary down counter with synchronous and asynchronous load and reset. Counter outputs only internally connected but ripple carry and zero detect outputs available.<\/p>\n<pre>       +---+--+---+\r\n   CLK |1  +--+ 16| VCC\r\n  \/RST |2       15| \/SLD\r\n\/CLKEN |3       14| \/RCO\r\n    P0 |4       13| P7\r\n    P1 |5 40103 12| P6\r\n    P2 |6       11| P5\r\n    P3 |7       10| P4\r\n   GND |8        9| \/ALD\r\n       +----------+\r\n<\/pre>\n<p><a name=\"40104\"><\/a><\/p>\n<h2>40104<\/h2>\n<p>4-bit 3-state bidirectional universal shift register.<\/p>\n<pre>    +---+--+---+             +---+---*---------------+\r\n OE |1  +--+ 16| VCC         | S1| S0| Function      |\r\n  D |2       15| Y0          +===+===*===============+\r\n P0 |3       14| Y1          | 0 | 0 | Reset         |\r\n P1 |4       13| Y2          | 0 | 1 | Shift right   |\r\n P2 |5 40104 12| Y3          | 1 | 0 | Shift left    |\r\n P3 |6       11| CLK         | 1 | 1 | Parallel load |\r\n  L |7       10| S1          +---+---*---------------+\r\nGND |8        9| S0\r\n    +----------+\r\n<\/pre>\n<p><a name=\"40105\"><\/a><\/p>\n<h2>40105<\/h2>\n<p>16&#215;4 3-state asynchronous FIFO with reset.<\/p>\n<pre>      +---+--+---+\r\n   OE |1  +--+ 16| VCC\r\n\/FULL |2       15| RD\r\n   WR |3       14| \/EMPTY\r\n   D0 |4       13| Q0\r\n   D1 |5 40105 12| Q1\r\n   D2 |6       11| Q2\r\n   D3 |7       10| Q3\r\n  GND |8        9| RST\r\n      +----------+\r\n<\/pre>\n<p><a name=\"40106\"><\/a><\/p>\n<h2>40106<\/h2>\n<p>Hex inverters with schmitt-trigger inputs.<br \/>\n0.9V typical input hysteresis at VCC=+5V and 2.3V at VCC=+10V.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\n 1A |1  +--+ 14| VCC         | A |\/Y |          \/Y = A\r\n\/1Y |2       13| 6A          +===*===+\r\n 2A |3       12| \/6Y         | 0 | 1 |\r\n\/2Y |4 40106 11| 5A          | 1 | 0 |\r\n 3A |5       10| \/5Y         +---*---+\r\n\/3Y |6        9| 4A\r\nGND |7        8| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"40107\"><\/a><\/p>\n<h2>40107<\/h2>\n<p>Dual 2-input open-collector NAND gates with buffered output.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n 1A |1  +--+  8| VCC         | A | B |\/Y |      \/Y = AB\r\n 1B |2        7| 2B          +===+===*===+\r\n\/1Y |3 40107  6| 2A          | 0 | 0 | Z |\r\nGND |4        5| \/2Y         | 0 | 1 | Z |\r\n    +----------+             | 1 | 0 | Z |\r\n                             | 1 | 1 | 0 |\r\n                             +---+---*---+\r\n<\/pre>\n<p><a name=\"40108\"><\/a><\/p>\n<h2>40108<\/h2>\n<p>4&#215;4-bit 3-state synchronous triple-port register file.<\/p>\n<pre>      +-----+--+-----+\r\n  1Q3 |1    +--+   24| VCC\r\n  1Q2 |2           23| 1Q1\r\n  1RD |3           22| 1Q0\r\n  2Q0 |4           21| 2RD\r\n  2Q1 |5           20| D0\r\n  2Q2 |6           19| D1\r\n  2Q3 |7   40108   18| D2\r\n  WA0 |8           17| D3\r\n  WA1 |9           16| WCLK\r\n 2RA1 |10          15| WR\r\n 2RA0 |11          14| 1RA1\r\n  GND |12          13| 1RA0\r\n      +--------------+\r\n<\/pre>\n<p><a name=\"40109\"><\/a><\/p>\n<h2>40109<\/h2>\n<p>Quad 3-state noninverting buffer\/level shifter.<br \/>\nVDD supplies the output stage, VCC the input stage.<\/p>\n<pre>    +---+--+---+             +---+---*-----+\r\nVCC |1  +--+ 16| VDD         | A | OE|  Y  |\r\n1OE |2       15| 4OE         +===+===*=====+\r\n 1A |3       14| 4A          | X | 0 |  Z  |\r\n 1Y |4       13| 4Y          | 0 | 1 | GND |\r\n 2Y |5 40109 12|             | 1 | 1 | VDD |\r\n 2A |6       11| 3Y          +---+---*-----+\r\n2OE |7       10| 3A\r\nGND |8        9| 3OE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"40110\"><\/a><\/p>\n<h2>40110<\/h2>\n<p>4-bit asynchronous decade up\/down counter with 7-segment decoder\/common- cathode LED driver, ripple carry and borrow, separate up and down clocks, clock enable and output latch.<\/p>\n<pre>       +---+--+---+\r\n    YA |1  +--+ 16| VCC\r\n    YG |2       15| YB\r\n    YF |3       14| YC\r\n\/CLKEN |4       13| YD\r\n   RST |5 40110 12| YE\r\n    LE |6       11| BORROW\r\n CLKDN |7       10| CARRY\r\n   GND |8        9| CLKUP\r\n       +----------+\r\n<\/pre>\n<p><a name=\"40147\"><\/a><\/p>\n<h2>40147<\/h2>\n<p>10-to-4 line noninverting priority encoder.<\/p>\n<pre>    +---+--+---+\r\n A4 |1  +--+ 16| VCC\r\n A5 |2       15| A0\r\n A6 |3       14| Y3\r\n A7 |4       13| A3\r\n A8 |5 40147 12| A2\r\n Y2 |6       11| A1\r\n Y1 |7       10| A9\r\nGND |8        9| Y0\r\n    +----------+\r\n<\/pre>\n<p><a name=\"40160\"><\/a><\/p>\n<h2>40160<\/h2>\n<p>4-bit synchronous decade counter with load, asynchronous reset, and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\n\/RST |1  +--+ 16| VCC\r\n CLK |2       15| RCO\r\n  P0 |3       14| Q0\r\n  P1 |4   74  13| Q1\r\n  P2 |5  160  12| Q2\r\n  P3 |6       11| Q3\r\n ENP |7       10| ENT\r\n GND |8        9| \/LOAD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"40161\"><\/a><\/p>\n<h2>40161<\/h2>\n<p>4-bit synchronous binary counter with load, asynchronous reset, and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\n\/RST |1  +--+ 16| VCC\r\n CLK |2       15| RCO\r\n  P0 |3       14| Q0\r\n  P1 |4   74  13| Q1\r\n  P2 |5  161  12| Q2\r\n  P3 |6       11| Q3\r\n ENP |7       10| ENT\r\n GND |8        9| \/LOAD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"40162\"><\/a><\/p>\n<h2>40162<\/h2>\n<p>4-bit synchronous decade counter with load, reset, and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\n\/RST |1  +--+ 16| VCC\r\n CLK |2       15| RCO\r\n  P0 |3       14| Q0\r\n  P1 |4   74  13| Q1\r\n  P2 |5  162  12| Q2\r\n  P3 |6       11| Q3\r\n ENP |7       10| ENT\r\n GND |8        9| \/LOAD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"40163\"><\/a><\/p>\n<h2>40163<\/h2>\n<p>4-bit synchronous binary counter with load, reset, and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\n\/RST |1  +--+ 16| VCC\r\n CLK |2       15| RCO\r\n  P0 |3       14| Q0\r\n  P1 |4   74  13| Q1\r\n  P2 |5  163  12| Q2\r\n  P3 |6       11| Q3\r\n ENP |7       10| ENT\r\n GND |8        9| \/LOAD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"40174\"><\/a><\/p>\n<h2>40174<\/h2>\n<p>6-bit D flip-flop with reset.<\/p>\n<pre>     +---+--+---+            +----+---+---*---+\r\n\/RST |1  +--+ 16| VCC        |\/RST|CLK| D | Q |\r\n  Q0 |2       15| Q6         +====+===+===*===+\r\n  D0 |3       14| D5         |  0 | X | X | 0 |\r\n  D1 |4   74  13| D4         |  1 | \/ | 0 | 0 |\r\n  Q1 |5  174  12| Q4         |  1 | \/ | 1 | 1 |\r\n  D2 |6       11| D3         |  1 |!\/ | X | - |\r\n  Q2 |7       10| Q3         +----+---+---*---+\r\n GND |8        9| CLK\r\n     +----------+\r\n<\/pre>\n<p><a name=\"40181\"><\/a><\/p>\n<h2>40181<\/h2>\n<p>4-bit 16-function arithmetic logic unit (ALU)<\/p>\n<pre>    +---+--+---+\r\n\/B0 |1  +--+ 24| VCC\r\n\/A0 |2       23| \/A1\r\n S3 |3       22| \/B1\r\n S2 |4       21| \/A2\r\n S1 |5       20| \/B2\r\n S0 |6   74  19| \/A3\r\nCIN |7  181  18| \/B3\r\n  M |8       17| \/G\r\n\/F0 |9       16| COUT\r\n\/F1 |10      15| \/P\r\n\/F2 |11      14| A=B\r\nGND |12      13| \/F3\r\n    +----------+\r\n<\/pre>\n<p><a name=\"40182\"><\/a><\/p>\n<h2>40182<\/h2>\n<p>Look-ahead carry generator Capable of anticipating a carry across four binary adders or group of adders.<br \/>\nCascadable to perform full look-ahead across n-bit adders.<\/p>\n<pre>    +---+--+---+\r\n\/G1 |1  +--+ 16| VCC\r\n\/P1 |2       15| \/P2\r\n\/G0 |3       14| \/G2\r\n\/P0 |4   74  13| Cn\r\n\/G3 |5  182  12| Cn+X\r\n\/P3 |6       11| Cn+Y\r\n \/P |7       10| \/G\r\nGND |8        9| Cn+Z\r\n    +----------+\r\n<\/pre>\n<p><a name=\"40192\"><\/a><\/p>\n<h2>40192<\/h2>\n<p>4-bit synchronous decade up\/down counter with asynchronous load and reset, and separate up and down clocks, carry and borrow outputs.<\/p>\n<pre>     +---+--+---+\r\n  P1 |1  +--+ 16| VCC\r\n  Q1 |2       15| P0\r\n  Q0 |3       14| RST\r\nDOWN |4   74  13| \/BORROW\r\n  UP |5  192  12| \/CARRY\r\n  Q2 |6       11| \/LOAD\r\n  Q3 |7       10| P2\r\n GND |8        9| P3\r\n     +----------+\r\n<\/pre>\n<p><a name=\"40193\"><\/a><\/p>\n<h2>40193<\/h2>\n<p>4-bit synchronous binary up\/down counter with asynchronous load and reset, and separate up and down clocks. Carry and borrow outputs.<\/p>\n<pre>     +---+--+---+\r\n  P1 |1  +--+ 16| VCC\r\n  Q1 |2       15| P0\r\n  Q0 |3       14| RST\r\nDOWN |4   74  13| \/BORROW\r\n  UP |5  193  12| \/CARRY\r\n  Q2 |6       11| \/LOAD\r\n  Q3 |7       10| P2\r\n GND |8        9| P3\r\n     +----------+\r\n<\/pre>\n<p><a name=\"40194\"><\/a><\/p>\n<h2>40194<\/h2>\n<p>4-bit bidirectional universal shift register with asynchronous reset.<\/p>\n<pre>     +---+--+---+            +---+---*---------------+\r\n\/RST |1  +--+ 16| VCC        | S1| S0| Function      |\r\n   D |2       15| Q0         +===+===*===============+\r\n  P0 |3       14| Q1         | 0 | 0 | Hold          |\r\n  P1 |4 40194 13| Q2         | 0 | 1 | Shift right   |\r\n  P2 |5 74194 12| Q3         | 1 | 0 | Shift left    |\r\n  P3 |6       11| CLK        | 1 | 1 | Parallel load |\r\n   L |7       10| S1         +---+---*---------------+\r\n GND |8        9| S0\r\n     +----------+\r\n<\/pre>\n<p><a name=\"40208\"><\/a><\/p>\n<h2>40208<\/h2>\n<p>4&#215;4-bit 3-state synchronous triple-port register file.<\/p>\n<pre>      +-----+--+-----+\r\n  1Q3 |1    +--+   24| VCC\r\n  1Q2 |2           23| 1Q1\r\n  1RD |3           22| 1Q0\r\n  2Q0 |4           21| 2RD\r\n  2Q1 |5           20| D0\r\n  2Q2 |6           19| D1\r\n  2Q3 |7   40108   18| D2\r\n  WA0 |8           17| D3\r\n  WA1 |9           16| WCLK\r\n 2RA1 |10          15| WR\r\n 2RA0 |11          14| 1RA1\r\n  GND |12          13| 1RA0\r\n      +--------------+\r\n<\/pre>\n<p><a name=\"40257\"><\/a><\/p>\n<h2>40257<\/h2>\n<p>8-to-4 line 3-state noninverting data selector\/multiplexer.<\/p>\n<pre>    +---+--+---+\r\n  S |1  +--+ 16| VCC\r\n1A0 |2       15| \/EN\r\n1A1 |3       14| 4A0\r\n 1Y |4   74  13| 4A1\r\n2A0 |5  257  12| 4Y\r\n2A1 |6       11| 3A0\r\n 2Y |7       10| 3A1\r\nGND |8        9| 3Y\r\n    +----------+<\/pre>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>4000 Dual 3-input NOR gates and inverter. +&#8212;+&#8211;+&#8212;+ ________ |1 +&#8211;+ 14| VCC \/1Y=1A+1B+1C |2 13| 3C 1A |3 12| 3B __ 1B |4 4000 11| 3A \/2Y=2A 1C |5 10| \/3Y \/1Y |6 9| \/2Y ________ GND |7 8| 2A \/3Y=3A+3B+3C +&#8212;&#8212;&#8212;-+ 4001 Quad 2-input NOR gates. +&#8212;+&#8211;+&#8212;+ +&#8212;+&#8212;*&#8212;+ ___ 1A |1 +&#8211;+ 14| &hellip; <\/p>\n<p class=\"link-more\"><a href=\"https:\/\/pcbjunkie.net\/index.php\/resources\/4000-series-ic-info-page\/\" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;4000 Series IC Info Page&#8221;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":277,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-302","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/pages\/302","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/comments?post=302"}],"version-history":[{"count":1,"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/pages\/302\/revisions"}],"predecessor-version":[{"id":303,"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/pages\/302\/revisions\/303"}],"up":[{"embeddable":true,"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/pages\/277"}],"wp:attachment":[{"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/media?parent=302"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}