{"id":295,"date":"2017-04-02T23:27:00","date_gmt":"2017-04-02T23:27:00","guid":{"rendered":"http:\/\/pcbjunkie.net\/?page_id=295"},"modified":"2017-04-02T23:32:59","modified_gmt":"2017-04-02T23:32:59","slug":"74-series-ics","status":"publish","type":"page","link":"https:\/\/pcbjunkie.net\/index.php\/resources\/74-series-ics\/","title":{"rendered":"74 Series ICs"},"content":{"rendered":"<h1>7400 series TTL IC&#8217;s<\/h1>\n<p><a name=\"7400\"><\/a><\/p>\n<h2>7400<\/h2>\n<p>Quad 2-input NAND gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3       12| 4A          | 0 | 0 | 1 |\r\n 2A |4  7400 11| \/4Y         | 0 | 1 | 1 |\r\n 2B |5       10| 3B          | 1 | 0 | 1 |\r\n\/2Y |6        9| 3A          | 1 | 1 | 0 |\r\nGND |7        8| \/3Y         +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7401\"><\/a><\/p>\n<h2>7401<\/h2>\n<p>Quad 2-input open-collector NAND gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n\/1Y |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = AB\r\n 1A |2       13| \/4Y         +===+===*===+\r\n 1B |3       12| 4B          | 0 | 0 | Z |\r\n\/2Y |4  7401 11| 4A          | 0 | 1 | Z |\r\n 2A |5       10| \/3Y         | 1 | 0 | Z |\r\n 2B |6        9| 3B          | 1 | 1 | 0 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7402\"><\/a><\/p>\n<h2>7402<\/h2>\n<p>Quad 2-input NOR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+           ___\r\n\/1Y |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = A+B\r\n 1A |2       13| \/4Y         +===+===*===+\r\n 1B |3       12| 4B          | 0 | 0 | 1 |\r\n\/2Y |4  7402 11| 4A          | 0 | 1 | 0 |\r\n 2A |5       10| \/3Y         | 1 | 0 | 0 |\r\n 2B |6        9| 3B          | 1 | 1 | 0 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7403\"><\/a><\/p>\n<h2>7403<\/h2>\n<p>Quad 2-input open-collector NAND gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3       12| 4A          | 0 | 0 | Z |\r\n 2A |4  7403 11| \/4Y         | 0 | 1 | Z |\r\n 2B |5       10| 3B          | 1 | 0 | Z |\r\n\/2Y |6        9| 3A          | 1 | 1 | 0 |\r\nGND |7        8| \/3Y         +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7404\"><\/a><\/p>\n<h2>7404<\/h2>\n<p>Hex inverters.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\n 1A |1  +--+ 14| VCC         | A |\/Y |          \/Y = A\r\n\/1Y |2       13| 6A          +===*===+\r\n 2A |3       12| \/6Y         | 0 | 1 |\r\n\/2Y |4  7404 11| 5A          | 1 | 0 |\r\n 3A |5       10| \/5Y         +---*---+\r\n\/3Y |6        9| 4A\r\nGND |7        8| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7405\"><\/a><\/p>\n<h2>7405<\/h2>\n<p>Hex open-collector inverters.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\n 1A |1  +--+ 14| VCC         | A |\/Y |          \/Y = A\r\n\/1Y |2       13| 6A          +===*===+\r\n 2A |3       12| \/6Y         | 0 | Z |\r\n\/2Y |4  7405 11| 5A          | 1 | 0 |\r\n 3A |5       10| \/5Y         +---*---+\r\n\/3Y |6        9| 4A\r\nGND |7        8| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7406\"><\/a><\/p>\n<h2>7406<\/h2>\n<p>Hex open-collector high-voltage inverters.<br \/>\nMaximum output voltage is 30V.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\n 1A |1  +--+ 14| VCC         | A |\/Y |          \/Y = A\r\n\/1Y |2       13| 6A          +===*===+\r\n 2A |3       12| \/6Y         | 0 | Z |\r\n\/2Y |4  7406 11| 5A          | 1 | 0 |\r\n 3A |5       10| \/5Y         +---*---+\r\n\/3Y |6        9| 4A\r\nGND |7        8| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7407\"><\/a><\/p>\n<h2>7407<\/h2>\n<p>Hex open-collector high-voltage buffers.<br \/>\nMaximum output voltage is 30V.<\/p>\n<pre>    +---+--+---+             +---*---+\r\n 1A |1  +--+ 14| VCC         | A | Y |           Y = A\r\n 1Y |2       13| 6A          +===*===+\r\n 2A |3       12| 6Y          | 0 | 0 |\r\n 2Y |4  7407 11| 5A          | 1 | Z |\r\n 3A |5       10| 5Y          +---*---+\r\n 3Y |6        9| 4A\r\nGND |7        8| 4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7408\"><\/a><\/p>\n<h2>7408<\/h2>\n<p>Quad 2-input AND gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | Y |       Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n 1Y |3       12| 4A          | 0 | 0 | 0 |\r\n 2A |4  7408 11| 4Y          | 0 | 1 | 0 |\r\n 2B |5       10| 3B          | 1 | 0 | 0 |\r\n 2Y |6        9| 3A          | 1 | 1 | 1 |\r\nGND |7        8| 3Y          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7409\"><\/a><\/p>\n<h2>7409<\/h2>\n<p>Quad 2-input open-collector AND gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | Y |       Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n 1Y |3       12| 4A          | 0 | 0 | 0 |\r\n 2A |4  7409 11| 4Y          | 0 | 1 | 0 |\r\n 2B |5       10| 3B          | 1 | 0 | 0 |\r\n 2Y |6        9| 3A          | 1 | 1 | Z |\r\nGND |7        8| 3Y          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7410\"><\/a><\/p>\n<h2>7410<\/h2>\n<p>Triple 3-input NAND gates.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+       ___\r\n 1A |1  +--+ 14| VCC         | A | B | C |\/Y |  \/Y = ABC\r\n 1B |2       13| 1C          +===+===+===*===+\r\n 2A |3       12| \/1Y         | 0 | X | X | 1 |\r\n 2B |4  7410 11| 3C          | 1 | 0 | X | 1 |\r\n 2C |5       10| 3B          | 1 | 1 | 0 | 1 |\r\n\/2Y |6        9| 3A          | 1 | 1 | 1 | 0 |\r\nGND |7        8| \/3Y         +---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7411\"><\/a><\/p>\n<h2>7411<\/h2>\n<p>Triple 3-input AND gates.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | C | Y |   Y = ABC\r\n 1B |2       13| 1C          +===+===+===*===+\r\n 2A |3       12| 1Y          | 0 | X | X | 0 |\r\n 2B |4  7411 11| 3C          | 1 | 0 | X | 0 |\r\n 2C |5       10| 3B          | 1 | 1 | 0 | 0 |\r\n 2Y |6        9| 3A          | 1 | 1 | 1 | 1 |\r\nGND |7        8| 3Y          +---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7412\"><\/a><\/p>\n<h2>7412<\/h2>\n<p>Triple 3-input open-collector NAND gates.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+       ___\r\n 1A |1  +--+ 14| VCC         | A | B | C |\/Y |  \/Y = ABC\r\n 1B |2       13| 1C          +===+===+===*===+\r\n 2A |3       12| \/1Y         | 0 | X | X | Z |\r\n 2B |4  7410 11| 3C          | 1 | 0 | X | Z |\r\n 2C |5       10| 3B          | 1 | 1 | 0 | Z |\r\n\/2Y |6        9| 3A          | 1 | 1 | 1 | 0 |\r\nGND |7        8| \/3Y         +---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7413\"><\/a><\/p>\n<h2>7413<\/h2>\n<p>Dual 4-input NAND gates with schmitt-trigger inputs.<br \/>\n0.8V typical input hysteresis at VCC=+5V.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+        ____\r\n 1A |1  +--+ 14| VCC         | A | B | C | D |\/Y |   \/Y = ABCD\r\n 1B |2       13| 2D          +===+===+===+===*===+\r\n    |3       12| 2C          | 0 | X | X | X | 1 |\r\n 1C |4  7413 11|             | 1 | 0 | X | X | 1 |\r\n 1D |5       10| 2B          | 1 | 1 | 0 | X | 1 |\r\n\/1Y |6        9| 2A          | 1 | 1 | 1 | 0 | 1 |\r\nGND |7        8| \/2Y         | 1 | 1 | 1 | 1 | 0 |\r\n    +----------+             +---+---+---+---*---+\r\n<\/pre>\n<p><a name=\"7414\"><\/a><\/p>\n<h2>7414<\/h2>\n<p>Hex inverters with schmitt-trigger inputs.<br \/>\n0.8V typical input hysteresis at VCC=+5V.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\n 1A |1  +--+ 14| VCC         | A |\/Y |          \/Y = A\r\n\/1Y |2       13| 6A          +===*===+\r\n 2A |3       12| \/6Y         | 0 | 1 |\r\n\/2Y |4  7414 11| 5A          | 1 | 0 |\r\n 3A |5       10| \/5Y         +---*---+\r\n\/3Y |6        9| 4A\r\nGND |7        8| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7415\"><\/a><\/p>\n<h2>7415<\/h2>\n<p>Triple 3-input open-collector AND gates.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | C | Y |   Y = ABC\r\n 1B |2       13| 1C          +===+===+===*===+\r\n 2A |3       12| 1Y          | 0 | X | X | 0 |\r\n 2B |4  7415 11| 3C          | 1 | 0 | X | 0 |\r\n 2C |5       10| 3B          | 1 | 1 | 0 | 0 |\r\n 2Y |6        9| 3A          | 1 | 1 | 1 | Z |\r\nGND |7        8| 3Y          +---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7416\"><\/a><\/p>\n<h2>7416<\/h2>\n<p>Hex open-collector high-voltage inverters.<br \/>\nMaximum output voltage is 15V.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\n 1A |1  +--+ 14| VCC         | A |\/Y |          \/Y = A\r\n\/1Y |2       13| 6A          +===*===+\r\n 2A |3       12| \/6Y         | 0 | Z |\r\n\/2Y |4  7416 11| 5A          | 1 | 0 |\r\n 3A |5       10| \/5Y         +---*---+\r\n\/3Y |6        9| 4A\r\nGND |7        8| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7417\"><\/a><\/p>\n<h2>7417<\/h2>\n<p>Hex open-collector high-voltage buffers.<br \/>\nMaximum output voltage is 15V.<\/p>\n<pre>    +---+--+---+             +---*---+\r\n 1A |1  +--+ 14| VCC         | A | Y |          Y = A\r\n 1Y |2       13| 6A          +===*===+\r\n 2A |3       12| 6Y          | 0 | 0 |\r\n 2Y |4  7417 11| 5A          | 1 | Z |\r\n 3A |5       10| 5Y          +---*---+\r\n 3Y |6        9| 4A\r\nGND |7        8| 4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7418\"><\/a><\/p>\n<h2>7418<\/h2>\n<p>Dual 4-input NAND gates with schmitt-trigger inputs.<br \/>\n0.8V typical input hysteresis at VCC=+5V.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+        ____\r\n 1A |1  +--+ 14| VCC         | A | B | C | D |\/Y |   \/Y = ABCD\r\n 1B |2       13| 2D          +===+===+===+===*===+\r\n    |3       12| 2C          | 0 | X | X | X | 1 |\r\n 1C |4  7418 11|             | 1 | 0 | X | X | 1 |\r\n 1D |5       10| 2B          | 1 | 1 | 0 | X | 1 |\r\n\/1Y |6        9| 2A          | 1 | 1 | 1 | 0 | 1 |\r\nGND |7        8| \/2Y         | 1 | 1 | 1 | 1 | 0 |\r\n    +----------+             +---+---+---+---*---+\r\n<\/pre>\n<p><a name=\"7419\"><\/a><\/p>\n<h2>7419<\/h2>\n<p>Hex inverters with schmitt-trigger line-receiver inputs.<br \/>\n0.8V typical input hysteresis at VCC=+5V.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\n 1A |1  +--+ 14| VCC         | A |\/Y |          \/Y = A\r\n\/1Y |2       13| 6A          +===*===+\r\n 2A |3       12| \/6Y         | 0 | 1 |\r\n\/2Y |4  7414 11| 5A          | 1 | 0 |\r\n 3A |5       10| \/5Y         +---*---+\r\n\/3Y |6        9| 4A\r\nGND |7        8| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7420\"><\/a><\/p>\n<h2>7420<\/h2>\n<p>Dual 4-input NAND gates.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+        ____\r\n 1A |1  +--+ 14| VCC         | A | B | C | D |\/Y |   \/Y = ABCD\r\n 1B |2       13| 2D          +===+===+===+===*===+\r\n    |3       12| 2C          | 0 | X | X | X | 1 |\r\n 1C |4  7420 11|             | 1 | 0 | X | X | 1 |\r\n 1D |5       10| 2B          | 1 | 1 | 0 | X | 1 |\r\n\/1Y |6        9| 2A          | 1 | 1 | 1 | 0 | 1 |\r\nGND |7        8| \/2Y         | 1 | 1 | 1 | 1 | 0 |\r\n    +----------+             +---+---+---+---*---+\r\n<\/pre>\n<p><a name=\"7421\"><\/a><\/p>\n<h2>7421<\/h2>\n<p>Dual 4-input AND gates.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | C | D | Y |    Y = ABCD\r\n 1B |2       13| 2D          +===+===+===+===*===+\r\n    |3       12| 2C          | 0 | X | X | X | 0 |\r\n 1C |4  7421 11|             | 1 | 0 | X | X | 0 |\r\n 1D |5       10| 2B          | 1 | 1 | 0 | X | 0 |\r\n 1Y |6        9| 2A          | 1 | 1 | 1 | 0 | 0 |\r\nGND |7        8| 2Y          | 1 | 1 | 1 | 1 | 1 |\r\n    +----------+             +---+---+---+---*---+\r\n<\/pre>\n<p><a name=\"7422\"><\/a><\/p>\n<h2>7422<\/h2>\n<p>Dual 4-input open-collector NAND gates.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+        ____\r\n 1A |1  +--+ 14| VCC         | A | B | C | D |\/Y |   \/Y = ABCD\r\n 1B |2       13| 2D          +===+===+===+===*===+\r\n    |3       12| 2C          | 0 | X | X | X | Z |\r\n 1C |4  7422 11|             | 1 | 0 | X | X | Z |\r\n 1D |5       10| 2B          | 1 | 1 | 0 | X | Z |\r\n\/1Y |6        9| 2A          | 1 | 1 | 1 | 0 | Z |\r\nGND |7        8| \/2Y         | 1 | 1 | 1 | 1 | 0 |\r\n    +----------+             +---+---+---+---*---+\r\n<\/pre>\n<p><a name=\"7424\"><\/a><\/p>\n<h2>7424<\/h2>\n<p>Quad 2-input NAND gates with schmitt-trigger line-receiver inputs.<br \/>\n0.8V typical input hysteresis at VCC=+5V.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3       12| 4A          | 0 | 0 | 1 |\r\n 2A |4  7424 11| \/4Y         | 0 | 1 | 1 |\r\n 2B |5       10| 3B          | 1 | 0 | 1 |\r\n\/2Y |6        9| 3A          | 1 | 1 | 0 |\r\nGND |7        8| \/3Y         +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7425\"><\/a><\/p>\n<h2>7425<\/h2>\n<p>Dual 4-input NOR gates with enable input.<\/p>\n<pre>    +---+--+---+                 __________\r\n 1A |1  +--+ 14| VCC         Y = G(A+B+C+D)\r\n 1B |2       13| 2D\r\n 1G |3       12| 2C\r\n 1C |4  7425 11| 2G\r\n 1D |5       10| 2B\r\n\/1Y |6        9| 2A\r\nGND |7        8| \/2Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7426\"><\/a><\/p>\n<h2>7426<\/h2>\n<p>Quad 2-input open-collector high-voltage NAND gates.<br \/>\nMaximum output voltage is 15V.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3       12| 4A          | 0 | 0 | Z |\r\n 2A |4  7426 11| \/4Y         | 0 | 1 | Z |\r\n 2B |5       10| 3B          | 1 | 0 | Z |\r\n\/2Y |6        9| 3A          | 1 | 1 | 0 |\r\nGND |7        8| \/3Y         +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7427\"><\/a><\/p>\n<h2>7427<\/h2>\n<p>Triple 3-input NOR gates.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+       _____\r\n 1A |1  +--+ 14| VCC         | A | B | C |\/Y |  \/Y = A+B+C\r\n 1B |2       13| 1C          +===+===+===*===+\r\n 2A |3       12| \/1Y         | 0 | 0 | 0 | 1 |\r\n 2B |4  7427 11| 3C          | 0 | 0 | 1 | 0 |\r\n 2C |5       10| 3B          | 0 | 1 | X | 0 |\r\n\/2Y |6        9| 3A          | 1 | X | X | 0 |\r\nGND |7        8| \/3Y         +---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7428\"><\/a><\/p>\n<h2>7428<\/h2>\n<p>Quad 2-input NOR gates with buffered outputs.<\/p>\n<pre>    +---+--+---+             +---+---*---+           ___\r\n\/1Y |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = A+B\r\n 1A |2       13| \/4Y         +===+===*===+\r\n 1B |3       12| 4B          | 0 | 0 | 1 |\r\n\/2Y |4  7428 11| 4A          | 0 | 1 | 0 |\r\n 2A |5       10| \/3Y         | 1 | 0 | 0 |\r\n 2B |6        9| 3B          | 1 | 1 | 0 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7430\"><\/a><\/p>\n<h2>7430<\/h2>\n<p>8-input NAND gate.<\/p>\n<pre>    +---+--+---+                 ________\r\n  A |1  +--+ 14| VCC        \/Y = ABCDEFGH\r\n  B |2       13|\r\n  C |3       12| H\r\n  D |4  7430 11| G\r\n  E |5       10|\r\n  F |6        9|\r\nGND |7        8| \/Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7431\"><\/a><\/p>\n<h2>7431<\/h2>\n<p>Hex delay elements.<br \/>\nTypical delays are 27.5ns (1,6), 46.5ns (2,5), 6ns (3,4). Improved output currents IoH=-1.2mA, IoL=24mA for gates 3 and 4.<\/p>\n<pre>    +---+--+---+                 _            _____\r\n 1A |1  +--+ 16| VCC        \/1Y=1A        \/4Y=4A.4B\r\n\/1Y |2       15| 6A\r\n 2A |3       14| \/6Y         2Y=2A         5Y=5A\r\n 2Y |4       13| 5A             _____          _\r\n 3A |5  7431 12| 5Y         \/3Y=3A.3B     \/6Y=6A\r\n 3B |6       11| 4B\r\n\/3Y |7       10| 4A\r\nGND |8        9| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7432\"><\/a><\/p>\n<h2>7432<\/h2>\n<p>Quad 2-input OR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | Y |       Y = A+B\r\n 1B |2       13| 4B          +===+===*===+\r\n 1Y |3       12| 4A          | 0 | 0 | 0 |\r\n 2A |4  7432 11| 4Y          | 0 | 1 | 1 |\r\n 2B |5       10| 3B          | 1 | 0 | 1 |\r\n 2Y |6        9| 3A          | 1 | 1 | 1 |\r\nGND |7        8| 3Y          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7433\"><\/a><\/p>\n<h2>7433<\/h2>\n<p>Quad 2-input open-collector NOR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+           ___\r\n\/1Y |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = A+B\r\n 1A |2       13| \/4Y         +===+===*===+\r\n 1B |3       12| 4B          | 0 | 0 | Z |\r\n\/2Y |4  7433 11| 4A          | 0 | 1 | 0 |\r\n 2A |5       10| \/3Y         | 1 | 0 | 0 |\r\n 2B |6        9| 3B          | 1 | 1 | 0 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7437\"><\/a><\/p>\n<h2>7437<\/h2>\n<p>Quad 2-input NAND gates with buffered output.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3       12| 4A          | 0 | 0 | 1 |\r\n 2A |4  7437 11| \/4Y         | 0 | 1 | 1 |\r\n 2B |5       10| 3B          | 1 | 0 | 1 |\r\n\/2Y |6        9| 3A          | 1 | 1 | 0 |\r\nGND |7        8| \/3Y         +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7438\"><\/a><\/p>\n<h2>7438<\/h2>\n<p>Quad 2-input open-collector NAND gates with buffered output.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3       12| 4A          | 0 | 0 | Z |\r\n 2A |4  7438 11| \/4Y         | 0 | 1 | Z |\r\n 2B |5       10| 3B          | 1 | 0 | Z |\r\n\/2Y |6        9| 3A          | 1 | 1 | 0 |\r\nGND |7        8| \/3Y         +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7440\"><\/a><\/p>\n<h2>7440<\/h2>\n<p>Dual 4-input NAND gates with buffered output.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+        ____\r\n 1A |1  +--+ 14| VCC         | A | B | C | D |\/Y |   \/Y = ABCD\r\n 1B |2       13| 2D          +===+===+===+===*===+\r\n    |3       12| 2C          | 0 | X | X | X | 1 |\r\n 1C |4  7440 11|             | 1 | 0 | X | X | 1 |\r\n 1D |5       10| 2B          | 1 | 1 | 0 | X | 1 |\r\n\/1Y |6        9| 2A          | 1 | 1 | 1 | 0 | 1 |\r\nGND |7        8| \/2Y         | 1 | 1 | 1 | 1 | 0 |\r\n    +----------+             +---+---+---+---*---+\r\n<\/pre>\n<p><a name=\"7442\"><\/a><\/p>\n<h2>7442<\/h2>\n<p>1-of-10 inverting decoder\/demultiplexer.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+---+---+---+\r\n\/Y0 |1  +--+ 16| VCC         | S3| S2| S1| S0|\/Y0|\/Y1|...|\/Y9|\r\n\/Y1 |2       15| S0          +===+===+===+===*===+===+===+===+\r\n\/Y2 |3       14| S1          | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |\r\n\/Y3 |4       13| S2          | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |\r\n\/Y4 |5  7442 12| S3          | . | . | . | . | 1 | 1 | . | 1 |\r\n\/Y5 |6       11| \/Y9         | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |\r\n\/Y6 |7       10| \/Y8         | 1 | 0 | 1 | X | 1 | 1 | 1 | 1 |\r\nGND |8        9| \/Y7         | 1 | 1 | X | X | 1 | 1 | 1 | 1 |\r\n    +----------+             +---+---+---+---*---+---+---+---+\r\n<\/pre>\n<p><a name=\"7446\"><\/a><a name=\"7447\"><\/a><\/p>\n<h2>7446, 7447<\/h2>\n<p>Open-collector BCD to 7-segment decoder\/common-anode LED driver with ripple blank input and output.<br \/>\n7446 has 30V outputs, 7447 has 15V outputs.<\/p>\n<pre>     +---+--+---+\r\n  A1 |1  +--+ 16| VCC\r\n  A2 |2       15| \/YF\r\n \/LT |3       14| \/YG\r\n\/RBO |4       13| \/YA\r\n\/RBI |5  7447 12| \/YB\r\n  A3 |6       11| \/YC\r\n  A0 |7       10| \/YD\r\n GND |8        9| \/YE\r\n     +----------+\r\n<\/pre>\n<p><a name=\"7448\"><\/a><\/p>\n<h2>7448<\/h2>\n<p>BCD to 7-segment decoder\/common-cathode LED driver with ripple blank input and output.<\/p>\n<pre>     +---+--+---+\r\n  A1 |1  +--+ 16| VCC\r\n  A2 |2       15| YF\r\n \/LT |3       14| YG\r\n\/RBO |4       13| YA\r\n\/RBI |5  7448 12| YB\r\n  A3 |6       11| YC\r\n  A0 |7       10| YD\r\n GND |8        9| YE\r\n     +----------+\r\n<\/pre>\n<h1>7451<\/h1>\n<p>2-wide 2-input and 2-wide 3-input AND-NOR gates.<\/p>\n<pre>    +---+--+---+                  _____________________\r\n 1A |1  +--+ 14| VCC        \/1Y = (1A.1B.1C)+(1D.1E.1F)\r\n 2A |2       13| 1B\r\n 2B |3       12| 1C               _______________\r\n 2C |4  7451 11| 1D         \/2Y = (2A.2B)+(2C.2D)\r\n 2D |5       10| 1E\r\n\/2Y |6        9| 1F\r\nGND |7        8| \/1Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7454\"><\/a><\/p>\n<h2>7454<\/h2>\n<p>4-wide 2\/3-input AND-NOR gate.<\/p>\n<pre>    +---+--+---+                 ___________________________\r\n  A |1  +--+ 14| VCC        \/Y = (A.B)+(C.D.E)+(F.G.H)+(J.K)\r\n  B |2       13| K\r\n  C |3       12| J\r\n  D |4  7454 11| H\r\n  E |5       10| G\r\n \/Y |6        9| F\r\nGND |7        8|\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7455\"><\/a><\/p>\n<h2>7455<\/h2>\n<p>2-wide 4-input AND-NOR gate.<\/p>\n<pre>    +---+--+---+                 ___________________\r\n  A |1  +--+ 14| VCC        \/Y = (A.B.C.D)+(E.F.G.H)\r\n  B |2       13| H\r\n  C |3       12| G\r\n  D |4  7455 11| F\r\n    |5       10| E\r\n    |6        9|\r\nGND |7        8| \/Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7457\"><\/a><\/p>\n<h2>7457<\/h2>\n<p>Frequency divider.<br \/>\nCan generate one second timing pulses from 60 Hz. Two &#8217;57 devices may be interconnected to give frequency division of 3600 to 1, 1800 to 1, 900 to 1, etc. Features a reset pin that is common to all three counters.<\/p>\n<pre>     +---+--+---+\r\nCLKB |1  +--+  8| QC\r\n VCC |2        7| QB\r\n  QA |3  7457  6| RST\r\n GND |4        5| CLKA\r\n     +----------+\r\n<\/pre>\n<p><a name=\"7458\"><\/a><\/p>\n<h2>7458<\/h2>\n<p>2-wide 2-input and 2-wide 3-input AND-OR gates.<\/p>\n<pre>    +---+--+---+\r\n 1A |1  +--+ 14| VCC         1Y = (1A.1B.1C)+(1D.1E.1F)\r\n 2A |2       13| 1B\r\n 2B |3       12| 1C\r\n 2C |4  7458 11| 1D          2Y = (2A.2B)+(2C.2D)\r\n 2D |5       10| 1E\r\n 2Y |6        9| 1F\r\nGND |7        8| 1Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7472\"><\/a><\/p>\n<h2>7472<\/h2>\n<p>J-K flip-flop with triple ANDed J an K inputs, set and reset.<\/p>\n<pre>     +---+--+---+            +--------+--------+---+----+----*---+---+\r\n     |1  +--+ 14| VCC        |J1.J2.J3|K1.K2.K3|CLK|\/SET|\/RST| Q |\/Q |\r\n\/RST |2       13| \/SET       +========+========+===+====+====*===+===+\r\n  J1 |3       12| CLK        |    X   |    X   | X |  0 |  0 | ? | ? |\r\n  J2 |4  7472 11| K3         |    X   |    X   | X |  0 |  1 | 1 | 0 |\r\n  J3 |5       10| K2         |    X   |    X   | X |  1 |  0 | 0 | 1 |\r\n  \/Q |6        9| K1         |    0   |    0   | \/ |  1 |  1 | - | - |\r\n GND |7        8| Q          |    0   |    1   | \/ |  1 |  1 | 0 | 1 |\r\n     +----------+            |    1   |    0   | \/ |  1 |  1 | 1 | 0 |\r\n                             |    1   |    1   | \/ |  1 |  1 |\/Q | Q |\r\n                             |    X   |    X   |!\/ |  1 |  1 | - | - |\r\n                             +--------+--------+---+----+----*---+---+\r\n<\/pre>\n<p><a name=\"7473\"><\/a><\/p>\n<h2>7473<\/h2>\n<p>Dual positive-edge-triggered J-K flip-flop with reset.<\/p>\n<pre>      +---+--+---+           +---+---+----+----*---+---+\r\n\/1CLK |1  +--+ 14| 1J        | J | K |\/CLK|\/RST| Q |\/Q |\r\n\/1RST |2       13| \/1Q       +===+===+====+====*===+===+\r\n   1K |3       12| 1Q        | X | X |  X |  0 | 0 | 1 |\r\n  VCC |4  7473 11| GND       | 0 | 0 |  \\ |  1 | - | - |\r\n\/2CLK |5       10| 2K        | 0 | 1 |  \\ |  1 | 0 | 1 |\r\n\/2RST |6        9| 2Q        | 1 | 0 |  \\ |  1 | 1 | 0 |\r\n   2J |7        8| \/2Q       | 1 | 1 |  \\ |  1 |\/Q | Q |\r\n      +----------+           | X | X | !\\ |  1 | - | - |\r\n                             +---+---+----+----*---+---+\r\n<\/pre>\n<p><a name=\"7474\"><\/a><\/p>\n<h2>7474<\/h2>\n<p>Dual D flip-flop with set and reset.<\/p>\n<pre>      +---+--+---+           +---+---+----+----*---+---+\r\n\/1RST |1  +--+ 14| VCC       | D |CLK|\/SET|\/RST| Q |\/Q |\r\n   1D |2       13| \/2RST     +===+===+====+====*===+===+\r\n 1CLK |3       12| 2D        | X | X |  0 |  0 | 1 | 1 |\r\n\/1SET |4  7474 11| 2CLK      | X | X |  0 |  1 | 1 | 0 |\r\n   1Q |5       10| \/2SET     | X | X |  1 |  0 | 0 | 1 |\r\n  \/1Q |6        9| 2Q        | 0 | \/ |  1 |  1 | 0 | 1 |\r\n  GND |7        8| \/2Q       | 1 | \/ |  1 |  1 | 1 | 0 |\r\n      +----------+           | X |!\/ |  1 |  1 | - | - |\r\n                             +---+---+----+----*---+---+\r\n<\/pre>\n<p><a name=\"7475\"><\/a><\/p>\n<h2>7475<\/h2>\n<p>Dual 2-bit transparent latches with complementary outputs.<\/p>\n<pre>     +---+--+---+\r\n\/1Q1 |1  +--+ 16| 1Q1\r\n 1D1 |2       15| 1Q2\r\n 1D2 |3       14| \/1Q2\r\n 2LE |4       13| 1LE\r\n VCC |5  7475 12| GND\r\n 2D1 |6       11| \/2Q1\r\n 2D2 |7       10| 2Q1\r\n\/2Q2 |8        9| 2Q2\r\n     +----------+\r\n<\/pre>\n<p><a name=\"7476\"><\/a><\/p>\n<h2>7476<\/h2>\n<p>Dual J-K flip-flops with set and reset.<\/p>\n<pre>      +---+--+---+           +---+---+---+----+----*---+---+\r\n 1CLK |1  +--+ 16| 1K        | J | K |CLK|\/SET|\/RST| Q |\/Q |\r\n\/1SET |2       15| 1Q        +===+===+===+====+====*===+===+\r\n\/1RST |3       14| \/1Q       | X | X | X |  0 |  0 | 0 | 0 |\r\n   1J |4       13| GND       | X | X | X |  0 |  1 | 1 | 0 |\r\n  VCC |5  7476 12| 2K        | X | X | X |  1 |  0 | 0 | 1 |\r\n 2CLK |6       11| 2Q        | 0 | 0 | \/ |  1 |  1 | - | - |\r\n\/2SET |7       10| \/2Q       | 0 | 1 | \/ |  1 |  1 | 0 | 1 |\r\n\/2RST |8        9| 2J        | 1 | 0 | \/ |  1 |  1 | 1 | 0 |\r\n      +----------+           | 1 | 1 | \/ |  1 |  1 |\/Q | Q |\r\n                             | X | X |!\/ |  1 |  1 | - | - |\r\n                             +---+---+---+----+----*---+---+\r\n<\/pre>\n<p><a name=\"7478\"><\/a><\/p>\n<h2>7478<\/h2>\n<p>Dual negative-edge-triggered J-K flip-flops with common clock, set and common reset.<\/p>\n<pre>      +---+--+---+           +---+---+----+----+----*---+---+\r\n \/CLK |1  +--+ 14| 1K        | J | K |\/CLK|\/SET|\/RST| Q |\/Q |\r\n\/1SET |2       13| 1Q        +===+===+====+====+====*===+===+\r\n   1J |3       12| \/1Q       | X | X |  X |  0 |  0 | ? | ? |\r\n  VCC |4  7478 11| GND       | X | X |  X |  0 |  1 | 1 | 0 |\r\n \/RST |5       10| 2J        | X | X |  X |  1 |  0 | 0 | 1 |\r\n\/2SET |6        9| \/2Q       | 0 | 0 |  \\ |  1 |  1 | - | - |\r\n   2K |7        8| 2Q        | 0 | 1 |  \\ |  1 |  1 | 0 | 1 |\r\n      +----------+           | 1 | 0 |  \\ |  1 |  1 | 1 | 0 |\r\n                             | 1 | 1 |  \\ |  1 |  1 |\/Q | Q |\r\n                             | X | X | !\\ |  1 |  1 | - | - |\r\n                             +---+---+----+----+----*---+---+\r\n<\/pre>\n<p><a name=\"7483\"><\/a><\/p>\n<h2>7483<\/h2>\n<p>4-bit binary full adder with fast carry.<\/p>\n<pre>    +---+--+---+\r\n A4 |1  +--+ 16| B4          S=A+B+CIN\r\n S3 |2       15| S4\r\n A3 |3       14| COUT\r\n B3 |4       13| CIN\r\nVCC |5  7483 12| GND\r\n S2 |6       11| B1\r\n B2 |7       10| A1\r\n A2 |8        9| S1\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7485\"><\/a><\/p>\n<h2>7485<\/h2>\n<p>4-bit noninverting magnitude comparator with cascade inputs.<\/p>\n<pre>     +---+--+---+\r\n  B3 |1  +--+ 16| VCC\r\nIA&lt;B |2       15| A3\r\nIA=B |3       14| B2\r\nIA&gt;B |4       13| A2\r\nOA&gt;B |5  7485 12| A1\r\nOA=B |6       11| B1\r\nOA&lt;B |7       10| A0\r\n GND |8        9| B0\r\n     +----------+\r\n<\/pre>\n<p><a name=\"7486\"><\/a><\/p>\n<h2>7486<\/h2>\n<p>Quad 2-input XOR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+                    _   _\r\n 1A |1  +--+ 14| VCC         | A | B | Y |       Y = A$B = (A.B)+(A.B)\r\n 1B |2       13| 4B          +===+===*===+\r\n 1Y |3       12| 4A          | 0 | 0 | 0 |\r\n 2A |4  7486 11| 4Y          | 0 | 1 | 1 |\r\n 2B |5       10| 3B          | 1 | 0 | 1 |\r\n 2Y |6        9| 3A          | 1 | 1 | 0 |\r\nGND |7        8| 3Y          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7490\"><\/a><\/p>\n<h2>7490<\/h2>\n<p>4-bit asynchronous decade counter with \/2 and \/5 sections, set(9) and reset.<\/p>\n<pre>      +---+--+---+\r\n\/CLK1 |1  +--+ 14| \/CLK0\r\n RST1 |2       13|\r\n RST2 |3       12| Q0\r\n      |4  7490 11| Q3\r\n  VCC |5       10| GND\r\n SET1 |6        9| Q1\r\n SET2 |7        8| Q2\r\n      +----------+\r\n<\/pre>\n<p><a name=\"7491\"><\/a><\/p>\n<h2>7491<\/h2>\n<p>8-bit serial-in serial-out shift register with two AND gated serial inputs and complementary outputs.<\/p>\n<pre>    +---+--+---+\r\n    |1  +--+ 14| \/Q7\r\n    |2       13| Q7\r\n    |3       12| D\r\n    |4  7491 11| E\r\nVCC |5       10| GND\r\n    |6        9| CLK\r\n    |7        8|\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7492\"><\/a><\/p>\n<h2>7492<\/h2>\n<p>4-bit asynchronous divide-by-twelve counter with \/2 and \/6 sections and reset.<\/p>\n<pre>      +---+--+---+\r\n\/CLK1 |1  +--+ 14| \/CLK0\r\n      |2       13|\r\n      |3       12| Q0\r\n      |4  7492 11| Q3\r\n  VCC |5       10| GND\r\n RST1 |6        9| Q1\r\n RST2 |7        8| Q2\r\n      +----------+\r\n<\/pre>\n<p><a name=\"7493\"><\/a><\/p>\n<h2>7493<\/h2>\n<p>4-bit asynchronous binary counter with \/2 and \/8 sections and reset.<\/p>\n<pre>      +---+--+---+\r\n\/CLK1 |1  +--+ 14| \/CLK0\r\n RST1 |2       13|\r\n RST2 |3       12| Q0\r\n      |4  7493 11| Q3\r\n  VCC |5       10| GND\r\n      |6        9| Q1\r\n      |7        8| Q2\r\n      +----------+\r\n<\/pre>\n<p><a name=\"7495\"><\/a><\/p>\n<h2>7495<\/h2>\n<p>4-bit universal shift register with separate shift and parallel-load clocks.<\/p>\n<pre>       +---+--+---+\r\n     D |1  +--+ 14| VCC\r\n    P0 |2       13| Q0\r\n    P1 |3       12| Q1\r\n    P2 |4  7495 11| Q2\r\n    P3 |5       10| Q3\r\nLD\/\/SH |6        9| SHCLK\r\n   GND |7        8| LDCLK\r\n       +----------+\r\n<\/pre>\n<p><a name=\"7496\"><\/a><\/p>\n<h2>7496<\/h2>\n<p>5-bit shift register with asynchronous reset and asynchronous preset inputs.<\/p>\n<pre>    +---+--+---+\r\nCLK |1  +--+ 16| \/RST\r\n P0 |2       15| Q0\r\n P1 |3       14| Q1\r\n P2 |4       13| Q2\r\nVCC |5  7496 12| GND\r\n P3 |6       11| Q3\r\n P4 |7       10| Q4\r\n PE |8        9| D\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7497\"><\/a><\/p>\n<h2>7497<\/h2>\n<p>6-bit synchronous binary rate multiplier.<br \/>\nCan perform fixed-rate or variable-rate frequency division. Output frequency is equal to input frequency multiplied by the rate input M and divided by 64.<\/p>\n<pre>      +---+--+---+\r\n   B1 |1  +--+ 16| VCC\r\n   B4 |2       15| B3\r\n   B5 |3       14| B2\r\n   B0 |4       13| RST\r\n    Z |5  7497 12| U\/CAS\r\n    Y |6       11| ENin\r\nENout |7       10| STRB\r\n  GND |8        9| CLK\r\n      +----------+\r\n<\/pre>\n<h2>74107<\/h2>\n<p>Dual negative-edge-triggered J-K flip-flops with reset.<\/p>\n<pre>    +---+--+---+             +---+---+----+----*---+---+\r\n 1J |1  +--+ 14| VCC         | J | K |\/CLK|\/RST| Q |\/Q |\r\n\/1Q |2       13| \/1RST       +===+===+====+====*===+===+\r\n 1Q |3   74  12| \/1CLK       | X | X |  X |  0 | 0 | 1 |\r\n 1K |4  107  11| 2K          | 0 | 0 |  \\ |  1 | - | - |\r\n 2Q |5       10| \/2RST       | 0 | 1 |  \\ |  1 | 0 | 1 |\r\n\/2Q |6        9| \/2CLK       | 1 | 0 |  \\ |  1 | 1 | 0 |\r\nGND |7        8| 2J          | 1 | 1 |  \\ |  1 |\/Q | Q |\r\n    +----------+             | X | X | !\\ |  1 | - | - |\r\n                             +---+---+----+----*---+---+\r\n<\/pre>\n<p><a name=\"74109\"><\/a><\/p>\n<h2>74109<\/h2>\n<p>Dual J-\/K flip-flops with set and reset.<\/p>\n<pre>      +---+--+---+           +---+---+---+----+----*---+---+\r\n\/1RST |1  +--+ 16| VCC       | J |\/K |CLK|\/SET|\/RST| Q |\/Q |\r\n   1J |2       15| \/2RST     +===+===+===+====+====*===+===+\r\n  \/1K |3       14| 2J        | X | X | X |  0 |  0 | 1 | 1 |\r\n 1CLK |4   74  13| \/2K       | X | X | X |  0 |  1 | 1 | 0 |\r\n\/1SET |5  109  12| 2CLK      | X | X | X |  1 |  0 | 0 | 1 |\r\n   1Q |6       11| \/2SET     | 0 | 0 | \/ |  1 |  1 | 0 | 1 |\r\n  \/1Q |7       10| 2Q        | 0 | 1 | \/ |  1 |  1 | - | - |\r\n  GND |8        9| \/2Q       | 1 | 0 | \/ |  1 |  1 |\/Q | Q |\r\n      +----------+           | 1 | 1 | \/ |  1 |  1 | 1 | 0 |\r\n                             | X | X |!\/ |  1 |  1 | - | - |\r\n                             +---+---+---+----+----*---+---+\r\n<\/pre>\n<p><a name=\"74112\"><\/a><\/p>\n<h2>74112<\/h2>\n<p>Dual negative-edge-triggered J-K flip-flops with set and reset.<\/p>\n<pre>      +---+--+---+           +---+---+----+----+----*---+---+\r\n\/1CLK |1  +--+ 16| VCC       | J | K |\/CLK|\/SET|\/RST| Q |\/Q |\r\n   1K |2       15| \/1RST     +===+===+====+====+====*===+===+\r\n   1J |3       14| \/2RST     | X | X |  X |  0 |  0 | 0 | 0 |\r\n\/1SET |4   74  13| \/2CLK     | X | X |  X |  0 |  1 | 1 | 0 |\r\n   1Q |5  112  12| 2K        | X | X |  X |  1 |  0 | 0 | 1 |\r\n  \/1Q |6       11| 2J        | 0 | 0 |  \\ |  1 |  1 | - | - |\r\n  \/2Q |7       10| \/2SET     | 0 | 1 |  \\ |  1 |  1 | 0 | 1 |\r\n  GND |8        9| 2Q        | 1 | 0 |  \\ |  1 |  1 | 1 | 0 |\r\n      +----------+           | 1 | 1 |  \\ |  1 |  1 |\/Q | Q |\r\n                             | X | X | !\\ |  1 |  1 | - | - |\r\n                             +---+---+----+----+----*---+---+\r\n<\/pre>\n<p><a name=\"74113\"><\/a><\/p>\n<h2>74113<\/h2>\n<p>Dual negative-edge-triggered J-K flip-flop with set.<\/p>\n<pre>      +---+--+---+           +---+---+----+----*---+---+\r\n\/1CLK |1  +--+ 14| VCC       | J | K |\/CLK|\/SET| Q |\/Q |\r\n   1K |2       13| \/2CLK     +===+===+====+====*===+===+\r\n   1J |3  74   12| 2K        | X | X |  X |  0 | 1 | 0 |\r\n\/1SET |4  113  11| 2J        | X | X |  X |  1 | 0 | 1 |\r\n   1Q |5       10| \/2SET     | 0 | 0 |  \\ |  1 | - | - |\r\n  \/1Q |6        9| 2Q        | 0 | 1 |  \\ |  1 | 0 | 1 |\r\n  GND |7        8| \/2Q       | 1 | 0 |  \\ |  1 | 1 | 0 |\r\n      +----------+           | 1 | 1 |  \\ |  1 |\/Q | Q |\r\n                             | X | X | !\\ |  1 | - | - |\r\n                             +---+---+----+----*---+---+\r\n<\/pre>\n<p><a name=\"74114\"><\/a><\/p>\n<h2>74114<\/h2>\n<p>Dual negative-edge-triggered J-K flip-flop with set, common clock and common reset.<\/p>\n<pre>      +---+--+---+           +---+---+----+----+----*---+---+\r\n \/RST |1  +--+ 14| VCC       | J | K |\/CLK|\/SET|\/RST| Q |\/Q |\r\n   1K |2       13| \/CLK      +===+===+====+====+====*===+===+\r\n   1J |3  74   12| 2K        | X | X |  X |  0 |  0 | ? | ? |\r\n\/1SET |4  114  11| 2J        | X | X |  X |  0 |  1 | 1 | 0 |\r\n   1Q |5       10| \/2SET     | X | X |  X |  1 |  0 | 0 | 1 |\r\n  \/1Q |6        9| 2Q        | 0 | 0 |  \\ |  1 |  1 | - | - |\r\n  GND |7        8| \/2Q       | 0 | 1 |  \\ |  1 |  1 | 0 | 1 |\r\n      +----------+           | 1 | 0 |  \\ |  1 |  1 | 1 | 0 |\r\n                             | 1 | 1 |  \\ |  1 |  1 |\/Q | Q |\r\n                             | X | X | !\\ |  1 |  1 | - | - |\r\n                             +---+---+----+----+----*---+---+\r\n<\/pre>\n<p><a name=\"74121\"><\/a><\/p>\n<h2>74121<\/h2>\n<p>Monostable multivibrator with Schmitt-trigger inputs.<br \/>\nProgrammable output pulse width from 40 ns to 20 seconds.<\/p>\n<pre>     +---+--+---+\r\n  \/Q |1  +--+ 14| VCC\r\n     |2       13|\r\n\/TR1 |3   74  12|\r\n\/TR2 |4  121  11| RCext\r\n  TR |5       10| Cext\r\n   Q |6        9| Rint\r\n GND |7        8|\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74122\"><\/a><\/p>\n<h2>74122<\/h2>\n<p>Retriggerable monostable multivibrator with overriding reset and integrated 10k timing resistor.<\/p>\n<pre>     +---+--+---+\r\n\/TR1 |1  +--+ 14| VCC\r\n\/TR2 |2       13| RCext\r\n TR1 |3   74  12|\r\n TR2 |4  122  11| Cext\r\n\/RST |5       10|\r\n  \/Q |6        9| Rint\r\n GND |7        8| Q\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74123\"><\/a><\/p>\n<h2>74123<\/h2>\n<p>Dual retriggerable monostable multivibrators with overriding reset.<\/p>\n<pre>       +---+--+---+\r\n  \/1TR |1  +--+ 16| VCC\r\n   1TR |2       15| 1RCext\r\n \/1RST |3       14| 1Cext\r\n   \/1Q |4   74  13| 1Q\r\n    2Q |5  123  12| \/2Q\r\n 2Cext |6       11| \/2RST\r\n2RCext |7       10| 2TR\r\n   GND |8        9| \/2TR\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74125\"><\/a><\/p>\n<h2>74125<\/h2>\n<p>Quad 3-state noninverting buffer with active low enables.<\/p>\n<pre>     +---+--+---+            +---+---*---+\r\n\/1OE |1  +--+ 14| VCC        | A |\/OE| Y |\r\n  1A |2       13| \/4OE       +===+===*===+\r\n  1Y |3   74  12| 4A         | 0 | 0 | 0 |\r\n\/2OE |4  125  11| 4Y         | 1 | 0 | 1 |\r\n  2A |5       10| \/3OE       | X | 1 | Z |\r\n  2Y |6        9| 3A         +---+---*---+\r\n GND |7        8| 3Y\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74126\"><\/a><\/p>\n<h2>74126<\/h2>\n<p>Quad 3-state noninverting buffer with active high enables.<\/p>\n<pre>    +---+--+---+             +---+---*---+\r\n1OE |1  +--+ 14| VCC         | A | OE| Y |\r\n 1A |2       13| 4OE         +===+===*===+\r\n 1Y |3   74  12| 4A          | X | 0 | Z |\r\n2OE |4  126  11| 4Y          | 0 | 1 | 0 |\r\n 2A |5       10| 3OE         | 1 | 1 | 1 |\r\n 2Y |6        9| 3A          +---+---*---+\r\nGND |7        8| 3Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74128\"><\/a><\/p>\n<h2>74128<\/h2>\n<p>Quad 2-input NOR gates\/line drivers.<\/p>\n<pre>    +---+--+---+             +---+---*---+           ___\r\n\/1Y |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = A+B\r\n 1A |2       13| \/4Y         +===+===*===+\r\n 1B |3       12| 4B          | 0 | 0 | 1 |\r\n\/2Y |4  7402 11| 4A          | 0 | 1 | 0 |\r\n 2A |5       10| \/3Y         | 1 | 0 | 0 |\r\n 2B |6        9| 3B          | 1 | 1 | 0 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74131\"><\/a><\/p>\n<h2>74131<\/h2>\n<p>1-of-8 inverting decoder\/demultiplexer with address register.<\/p>\n<pre>     +---+--+---+\r\n  S0 |1  +--+ 16| VCC\r\n  S1 |2       15| \/Y0\r\n  S2 |3       14| \/Y1\r\n CLK |4   74  13| \/Y2\r\n\/EN2 |5  131  12| \/Y3\r\n EN1 |6       11| \/Y4\r\n \/Y7 |7       10| \/Y5\r\n GND |8        9| \/Y6\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74132\"><\/a><\/p>\n<h2>74132<\/h2>\n<p>Quad 2-input NAND gates with schmitt-trigger inputs.<br \/>\n0.8V typical input hysteresis at VCC=+5V.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3       12| 4A          | 0 | 0 | 1 |\r\n 2A |4 74132 11| \/4Y         | 0 | 1 | 1 |\r\n 2B |5       10| 3B          | 1 | 0 | 1 |\r\n\/2Y |6        9| 3A          | 1 | 1 | 0 |\r\nGND |7        8| \/3Y         +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74133\"><\/a><\/p>\n<h2>74133<\/h2>\n<p>13-input NAND gate.<\/p>\n<pre>    +---+--+---+                 _____________\r\n  A |1  +--+ 16| VCC        \/Y = ABCDEFGHIJKLM\r\n  B |2       15| M\r\n  C |3       14| L\r\n  D |4   74  13| K\r\n  E |5  133  12| J\r\n  F |6       11| I\r\n  G |7       10| H\r\nGND |8        9| \/Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74136\"><\/a><\/p>\n<h2>74136<\/h2>\n<p>Quad 2-input open-collector XOR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+                    _   _\r\n 1A |1  +--+ 14| VCC         | A | B | Y |       Y = A$B = (A.B)+(A.B)\r\n 1B |2       13| 4B          +===+===*===+\r\n 1Y |3       12| 4A          | 0 | 0 | 0 |\r\n 2A |4 74136 11| 4Y          | 0 | 1 | Z |\r\n 2B |5       10| 3B          | 1 | 0 | Z |\r\n 2Y |6        9| 3A          | 1 | 1 | 0 |\r\nGND |7        8| 3Y          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74137\"><\/a><\/p>\n<h2>74137<\/h2>\n<p>1-of-8 inverting decoder\/demultiplexer with address latches.<\/p>\n<pre>     +---+--+---+\r\n  S0 |1  +--+ 16| VCC\r\n  S1 |2       15| \/Y0\r\n  S2 |3       14| \/Y1\r\n \/LE |4   74  13| \/Y2\r\n\/EN2 |5  137  12| \/Y3\r\n EN1 |6       11| \/Y4\r\n \/Y7 |7       10| \/Y5\r\n GND |8        9| \/Y6\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74138\"><\/a><\/p>\n<h2>74138<\/h2>\n<p>1-of-8 inverting decoder\/demultiplexer.<\/p>\n<pre>     +---+--+---+            +---+----+----+---+---+---*---+---+---+---+\r\n  S0 |1  +--+ 16| VCC        |EN1|\/EN2|\/EN3| S2| S1| S0|\/Y0|\/Y1|...|\/Y7|\r\n  S1 |2       15| \/Y0        +===+====+====+===+===+===*===+===+===+===+\r\n  S2 |3       14| \/Y1        | 0 | X  |  X | X | X | X | 1 | 1 | 1 | 1 |\r\n\/EN3 |4   74  13| \/Y2        | 1 | 1  |  X | X | X | X | 1 | 1 | 1 | 1 |\r\n\/EN2 |5  138  12| \/Y3        | 1 | 0  |  1 | X | X | X | 1 | 1 | 1 | 1 |\r\n EN1 |6       11| \/Y4        | 1 | 0  |  0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |\r\n \/Y7 |7       10| \/Y5        | 1 | 0  |  0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |\r\n GND |8        9| \/Y6        | 1 | 0  |  0 | . | . | . | 1 | 1 | . | 1 |\r\n     +----------+            | 1 | 0  |  0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |\r\n                             +---+----+----+---+---+---*---+---+---+---+\r\n<\/pre>\n<p><a name=\"74139\"><\/a><\/p>\n<h2>74139<\/h2>\n<p>Dual 1-of-4 inverting decoder\/demultiplexer.<\/p>\n<pre>     +---+--+---+            +---+---+---*---+---+---+---+\r\n\/1EN |1  +--+ 16| VCC        |\/EN| S1| S0|\/Y0|\/Y1|\/Y2|\/Y3|\r\n 1S0 |2       15| \/2EN       +===+===+===*===+===+===+===+\r\n 1S1 |3       14| 2S0        | 1 | X | X | 1 | 1 | 1 | 1 |\r\n\/1Y0 |4   74  13| 2S1        | 0 | 0 | 0 | 0 | 1 | 1 | 1 |\r\n\/1Y1 |5  139  12| \/2Y0       | 0 | 0 | 1 | 1 | 0 | 1 | 1 |\r\n\/1Y2 |6       11| \/2Y1       | 0 | 1 | 0 | 1 | 1 | 0 | 1 |\r\n\/1Y3 |7       10| \/2Y2       | 0 | 1 | 1 | 1 | 1 | 1 | 0 |\r\n GND |8        9| \/2Y3       +---+---+---*---+---+---+---+\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74140\"><\/a><\/p>\n<h2>74140<\/h2>\n<p>Dual 4-input NAND gates\/50R line drivers.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+        ____\r\n 1A |1  +--+ 14| VCC         | A | B | C | D |\/Y |   \/Y = ABCD\r\n 1B |2       13| 2D          +===+===+===+===*===+\r\n    |3   74  12| 2C          | 0 | X | X | X | 1 |\r\n 1C |4  140  11|             | 1 | 0 | X | X | 1 |\r\n 1D |5       10| 2B          | 1 | 1 | 0 | X | 1 |\r\n\/1Y |6        9| 2A          | 1 | 1 | 1 | 0 | 1 |\r\nGND |7        8| \/2Y         | 1 | 1 | 1 | 1 | 0 |\r\n    +----------+             +---+---+---+---*---+\r\n<\/pre>\n<p><a name=\"74141\"><\/a><\/p>\n<h2>74141<\/h2>\n<p>1-of-10 inverting decoder\/demultiplexer.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+---+---+---+\r\n\/Y8 |1  +--+ 16| \/Y0         | S3| S2| S1| S0|\/Y0|\/Y1|...|\/Y9|\r\n\/Y9 |2       15| \/Y1         +===+===+===+===*===+===+===+===+\r\n S0 |3       14| \/Y5         | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |\r\n S3 |4   74  13| \/Y4         | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |\r\nVCC |5  141  12| GND         | . | . | . | . | 1 | 1 | . | 1 |\r\n S1 |6       11| \/Y6         | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |\r\n S2 |7       10| \/Y7         | 1 | 0 | 1 | X | 1 | 1 | 1 | 1 |\r\n\/Y2 |8        9| \/Y3         | 1 | 1 | X | X | 1 | 1 | 1 | 1 |\r\n    +----------+             +---+---+---+---*---+---+---+---+\r\n<\/pre>\n<p><a name=\"74145\"><\/a><\/p>\n<h2>74145<\/h2>\n<p>1-of-10 open-collector inverting decoder\/demultiplexer.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+---+---+---+\r\n\/Y0 |1  +--+ 16| VCC         | S3| S2| S1| S0|\/Y0|\/Y1|...|\/Y9|\r\n\/Y1 |2       15| S0          +===+===+===+===*===+===+===+===+\r\n\/Y2 |3       14| S1          | 0 | 0 | 0 | 0 | 0 | Z | Z | Z |\r\n\/Y3 |4   74  13| S2          | 0 | 0 | 0 | 1 | Z | 0 | Z | Z |\r\n\/Y4 |5  145  12| S3          | . | . | . | . | Z | Z | . | Z |\r\n\/Y5 |6       11| \/Y9         | 1 | 0 | 0 | 1 | Z | Z | Z | 0 |\r\n\/Y6 |7       10| \/Y8         | 1 | 0 | 1 | X | Z | Z | Z | Z |\r\nGND |8        9| \/Y7         | 1 | 1 | X | X | Z | Z | Z | Z |\r\n    +----------+             +---+---+---+---*---+---+---+---+\r\n<\/pre>\n<p><a name=\"74147\"><\/a><\/p>\n<h2>74147<\/h2>\n<p>10-to-4 line inverting priority encoder.<\/p>\n<pre>    +---+--+---+\r\n\/A4 |1  +--+ 16| VCC\r\n\/A5 |2       15|\r\n\/A6 |3       14| Y3\r\n\/A7 |4   74  13| \/A3\r\n\/A8 |5  147  12| \/A2\r\n Y2 |6       11| \/A1\r\n Y1 |7       10| \/A9\r\nGND |8        9| Y0\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74148\"><\/a><\/p>\n<h2>74148<\/h2>\n<p>8-to-3 line inverting priority encoder with cascade inputs.<\/p>\n<pre>    +---+--+---+\r\n\/A4 |1  +--+ 16| VCC\r\n\/A5 |2       15| \/EO\r\n\/A6 |3       14| \/GS\r\n\/A7 |4   74  13| \/A3\r\n\/EI |5  148  12| \/A2\r\n Y2 |6       11| \/A1\r\n Y1 |7       10| \/A0\r\nGND |8        9| Y0\r\n    +----------+<\/pre>\n<p>&nbsp;<\/p>\n<h2>74150<\/h2>\n<p>16-to-1 line inverting data selector\/multiplexer.<\/p>\n<pre>    +---+--+---+\r\n D7 |1  +--+ 24| VCC\r\n D6 |2       23| D8\r\n D5 |3       22| D9\r\n D4 |4       21| D10\r\n D3 |5       20| D11\r\n D2 |6   74  19| D12\r\n D1 |7  150  18| D13\r\n D0 |8       17| D14\r\n\/EN |9       16| D15\r\n \/Y |10      15| S0\r\n S3 |11      14| S1\r\nGND |12      13| S2\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74151\"><\/a><\/p>\n<h2>74151<\/h2>\n<p>8-to-1 line data selector\/multiplexer with complementary outputs.<\/p>\n<pre>    +---+--+---+\r\n D3 |1  +--+ 16| VCC\r\n D2 |2       15| D4\r\n D1 |3       14| D5\r\n D0 |4   74  13| D6\r\n  Y |5  151  12| D7\r\n \/Y |6       11| S0\r\n\/EN |7       10| S1\r\nGND |8        9| S2\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74152\"><\/a><\/p>\n<h2>74152<\/h2>\n<p>8-to-1 line inverting data selector\/multiplexer.<\/p>\n<pre>    +---+--+---+\r\n A4 |1  +--+ 14| VCC\r\n A3 |2       13| A5\r\n A2 |3   74  12| A6\r\n A1 |4  152  11| A7\r\n A0 |5       10| S0\r\n \/Y |6        9| S1\r\nGND |7        8| S1\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74153\"><\/a><\/p>\n<h2>74153<\/h2>\n<p>8-to-2 line noninverting data selector\/multiplexer with separate enables.<\/p>\n<pre>     +---+--+---+\r\n\/1EN |1  +--+ 16| VCC\r\n  S1 |2       15| \/2EN\r\n 1A3 |3       14| S0\r\n 1A2 |4   74  13| 2A3\r\n 1A1 |5  153  12| 2A2\r\n 1A0 |6       11| 2A1\r\n  1Y |7       10| 2A0\r\n GND |8        9| 2Y\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74154\"><\/a><\/p>\n<h2>74154<\/h2>\n<p>1-of-16 inverting decoder\/demultiplexer.<\/p>\n<pre>     +---+--+---+\r\n \/Y0 |1  +--+ 24| VCC\r\n \/Y1 |2       23| S0\r\n \/Y2 |3       22| S1\r\n \/Y3 |4       21| S2\r\n \/Y4 |5       20| S3\r\n \/Y5 |6   74  19| \/EN2\r\n \/Y6 |7  154  18| \/EN1\r\n \/Y7 |8       17| \/Y15\r\n \/Y8 |9       16| \/Y14\r\n \/Y9 |10      15| \/Y13\r\n\/Y10 |11      14| \/Y12\r\n GND |12      13| \/Y11\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74155\"><\/a><\/p>\n<h2>74155<\/h2>\n<p>2-of-8 inverting decoder\/demultiplexer with separate enables.<\/p>\n<pre>      +---+--+---+\r\n 1EN1 |1  +--+ 16| VCC\r\n\/1EN2 |2       15| \/2EN1\r\n   S1 |3       14| \/2EN2\r\n \/1Y3 |4   74  13| S0\r\n \/1Y2 |5  155  12| \/2Y3\r\n \/1Y1 |6       11| \/2Y2\r\n \/1Y0 |7       10| \/2Y1\r\n  GND |8        9| \/2Y0\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74156\"><\/a><\/p>\n<h2>74156<\/h2>\n<p>2-of-8 open-collector inverting decoder\/demultiplexer with separate enables.<\/p>\n<pre>      +---+--+---+\r\n 1EN1 |1  +--+ 16| VCC\r\n\/1EN2 |2       15| \/2EN1\r\n   S1 |3       14| \/2EN2\r\n \/1Y3 |4   74  13| S0\r\n \/1Y2 |5  156  12| \/2Y3\r\n \/1Y1 |6       11| \/2Y2\r\n \/1Y0 |7       10| \/2Y1\r\n  GND |8        9| \/2Y0\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74157\"><\/a><\/p>\n<h2>74157<\/h2>\n<p>8-to-4 line noninverting data selector\/multiplexer.<\/p>\n<pre>    +---+--+---+\r\n  S |1  +--+ 16| VCC\r\n1A0 |2       15| \/EN\r\n1A1 |3       14| 4A0\r\n 1Y |4   74  13| 4A1\r\n2A0 |5  157  12| 4Y\r\n2A1 |6       11| 3A0\r\n 2Y |7       10| 3A1\r\nGND |8        9| 3Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74158\"><\/a><\/p>\n<h2>74158<\/h2>\n<p>4-of-8 inverting decoder\/demultiplexer.<\/p>\n<pre>    +---+--+---+\r\n  S |1  +--+ 16| VCC\r\n1A0 |2       15| \/EN\r\n1A1 |3       14| 4A0\r\n\/1Y |4   74  13| 4A1\r\n2A0 |5  158  12| \/4Y\r\n2A1 |6       11| 3A0\r\n\/2Y |7       10| 3A1\r\nGND |8        9| \/3Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74159\"><\/a><\/p>\n<h2>74159<\/h2>\n<p>1-of-16 open-collector inverting decoder\/demultiplexer.<\/p>\n<pre>     +---+--+---+\r\n \/Y0 |1  +--+ 24| VCC\r\n \/Y1 |2       23| S0\r\n \/Y2 |3       22| S1\r\n \/Y3 |4       21| S2\r\n \/Y4 |5       20| S3\r\n \/Y5 |6   74  19| \/EN2\r\n \/Y6 |7  159  18| \/EN1\r\n \/Y7 |8       17| \/Y15\r\n \/Y8 |9       16| \/Y14\r\n \/Y9 |10      15| \/Y13\r\n\/Y10 |11      14| \/Y12\r\n GND |12      13| \/Y11\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74160\"><\/a><\/p>\n<h2>74160<\/h2>\n<p>4-bit synchronous decade counter with load, asynchronous reset, and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\n\/RST |1  +--+ 16| VCC\r\n CLK |2       15| RCO\r\n  P0 |3       14| Q0\r\n  P1 |4   74  13| Q1\r\n  P2 |5  160  12| Q2\r\n  P3 |6       11| Q3\r\n ENP |7       10| ENT\r\n GND |8        9| \/LOAD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74161\"><\/a><\/p>\n<h2>74161<\/h2>\n<p>4-bit synchronous binary counter with load, asynchronous reset, and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\n\/RST |1  +--+ 16| VCC\r\n CLK |2       15| RCO\r\n  P0 |3       14| Q0\r\n  P1 |4   74  13| Q1\r\n  P2 |5  161  12| Q2\r\n  P3 |6       11| Q3\r\n ENP |7       10| ENT\r\n GND |8        9| \/LOAD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74162\"><\/a><\/p>\n<h2>74162<\/h2>\n<p>4-bit synchronous decade counter with load, reset, and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\n\/RST |1  +--+ 16| VCC\r\n CLK |2       15| RCO\r\n  P0 |3       14| Q0\r\n  P1 |4   74  13| Q1\r\n  P2 |5  162  12| Q2\r\n  P3 |6       11| Q3\r\n ENP |7       10| ENT\r\n GND |8        9| \/LOAD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74163\"><\/a><\/p>\n<h2>74163<\/h2>\n<p>4-bit synchronous binary counter with load, reset, and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\n\/RST |1  +--+ 16| VCC\r\n CLK |2       15| RCO\r\n  P0 |3       14| Q0\r\n  P1 |4   74  13| Q1\r\n  P2 |5  163  12| Q2\r\n  P3 |6       11| Q3\r\n ENP |7       10| ENT\r\n GND |8        9| \/LOAD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74164\"><\/a><\/p>\n<h2>74164<\/h2>\n<p>8-bit serial-in parallel-out shift register with asynchronous reset and two AND gated serial inputs.<\/p>\n<pre>    +---+--+---+\r\n  D |1  +--+ 14| VCC\r\n  E |2       13| Q7\r\n Q0 |3   74  12| Q6\r\n Q1 |4  164  11| Q5\r\n Q2 |5       10| Q4\r\n Q3 |6        9| \/RST\r\nGND |7        8| CLK\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74165\"><\/a><\/p>\n<h2>74165<\/h2>\n<p>8-bit parallel-in serial-out shift register with asynchronous parallel load and two OR gated clock inputs.<\/p>\n<pre>       +---+--+---+\r\nSH\/\/LD |1  +--+ 16| VCC\r\n  CLK1 |2       15| CLK2\r\n    P4 |3       14| P3\r\n    P5 |4   74  13| P2\r\n    P6 |5  165  12| P1\r\n    P7 |6       11| P0\r\n   \/Q7 |7       10| D\r\n   GND |8        9| Q7\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74166\"><\/a><\/p>\n<h2>74166<\/h2>\n<p>8-bit parallel-in serial-out shift register with asynchronous reset and two OR gated clock inputs.<\/p>\n<pre>     +---+--+---+\r\n   D |1  +--+ 16| VCC\r\n  P0 |2       15| SH\/\/LD\r\n  P1 |3       14| P7\r\n  P2 |4   74  13| Q7\r\n  P3 |5  166  12| P6\r\nCLK1 |6       11| P5\r\nCLK2 |7       10| P4\r\n GND |8        9| \/RST\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74167\"><\/a><\/p>\n<h2>74167<\/h2>\n<p>4-bit synchronous decade rate multiplier.<br \/>\nCan perform fixed-rate or variable-rate frequency division. Output frequency is equal to input frequency multiplied by the rate input M and divided by 10.<\/p>\n<pre>      +---+--+---+\r\n      |1  +--+ 16| VCC\r\n   B2 |2       15| B1\r\n   B3 |3       14| B0\r\nSET-9 |4   74  13| RST\r\n    Z |5  167  12| U\/CAS\r\n    Y |6       11| ENin\r\nENout |7       10| STRB\r\n  GND |8        9| CLK\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74168\"><\/a><\/p>\n<h2>74168<\/h2>\n<p>4-bit synchronous decade up\/down counter with load and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\nU\/\/D |1  +--+ 16| VCC\r\n CLK |2       15| \/RCO\r\n  P0 |3       14| Q0\r\n  P1 |4   74  13| Q1\r\n  P2 |5  168  12| Q2\r\n  P3 |6       11| Q3\r\n\/ENP |7       10| \/ENT\r\n GND |8        9| \/LOAD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74169\"><\/a><\/p>\n<h2>74169<\/h2>\n<p>4-bit synchronous binary up\/down counter with load and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\nU\/\/D |1  +--+ 16| VCC\r\n CLK |2       15| \/RCO\r\n  P0 |3       14| Q0\r\n  P1 |4   74  13| Q1\r\n  P2 |5  169  12| Q2\r\n  P3 |6       11| Q3\r\n\/ENP |7       10| \/ENT\r\n GND |8        9| \/LOAD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74170\"><\/a><\/p>\n<h2>74170<\/h2>\n<p>4&#215;4-bit open-collector dual-port register file.<\/p>\n<pre>    +---+--+---+\r\n D2 |1  +--+ 16| VCC\r\n D3 |2       15| D1\r\n D4 |3       14| WA0\r\nRA1 |4   74  13| WA1\r\nRA0 |5  170  12| \/WR\r\n Q4 |6       11| \/RD\r\n Q3 |7       10| Q1\r\nGND |8        9| Q2\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74173\"><\/a><\/p>\n<h2>74173<\/h2>\n<p>4-bit 3-state D flip-flop with reset, dual clock enables and dual output enables.<\/p>\n<pre>     +---+--+---+\r\n\/OE1 |1  +--+ 16| VCC\r\n\/OE2 |2       15| RST\r\n  Q0 |3       14| D0\r\n  Q1 |4   74  13| D1\r\n  Q2 |5  173  12| D2\r\n  Q3 |6       11| D3\r\n CLK |7       10| \/CLKEN1\r\n GND |8        9| \/CLKEN2\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74174\"><\/a><\/p>\n<h2>74174<\/h2>\n<p>6-bit D flip-flop with reset.<\/p>\n<pre>     +---+--+---+            +----+---+---*---+\r\n\/RST |1  +--+ 16| VCC        |\/RST|CLK| D | Q |\r\n  Q0 |2       15| Q6         +====+===+===*===+\r\n  D0 |3       14| D5         |  0 | X | X | 0 |\r\n  D1 |4   74  13| D4         |  1 | \/ | 0 | 0 |\r\n  Q1 |5  174  12| Q4         |  1 | \/ | 1 | 1 |\r\n  D2 |6       11| D3         |  1 |!\/ | X | - |\r\n  Q2 |7       10| Q3         +----+---+---*---+\r\n GND |8        9| CLK\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74175\"><\/a><\/p>\n<h2>74175<\/h2>\n<p>4-bit D flip-flop with complementary outputs and reset.<\/p>\n<pre>     +---+--+---+            +----+---+---*---+---+\r\n\/RST |1  +--+ 16| VCC        |\/RST|CLK| D | Q |\/Q |\r\n  Q1 |2       15| Q4         +====+===+===*===+===+\r\n \/Q1 |3       14| \/Q4        |  0 | X | X | 0 | 1 |\r\n  D1 |4   74  13| D4         |  1 | \/ | 0 | 0 | 1 |\r\n  D2 |5  175  12| D3         |  1 | \/ | 1 | 1 | 0 |\r\n \/Q2 |6       11| \/Q3        |  1 |!\/ | X | - | - |\r\n  Q2 |7       10| Q3         +----+---+---*---+---+\r\n GND |8        9| CLK\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74180\"><\/a><\/p>\n<h2>74180<\/h2>\n<p>8-bit odd\/even parity generator\/checker with cascade inputs.<\/p>\n<pre>      +---+--+---+\r\n   A0 |1  +--+ 14| VCC\r\n   A1 |2       13| A7\r\n CASE |3   74  12| A6\r\n CASO |4  180  11| A5\r\n EVEN |5       10| A4\r\n  ODD |6        9| A3\r\n  GND |7        8| A2\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74181\"><\/a><\/p>\n<h2>74181<\/h2>\n<p>4-bit 16-function arithmetic logic unit (ALU)<\/p>\n<pre>    +---+--+---+\r\n\/B0 |1  +--+ 24| VCC\r\n\/A0 |2       23| \/A1\r\n S3 |3       22| \/B1\r\n S2 |4       21| \/A2\r\n S1 |5       20| \/B2\r\n S0 |6   74  19| \/A3\r\nCIN |7  181  18| \/B3\r\n  M |8       17| \/G\r\n\/F0 |9       16| COUT\r\n\/F1 |10      15| \/P\r\n\/F2 |11      14| A=B\r\nGND |12      13| \/F3\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74182\"><\/a><\/p>\n<h2>74182<\/h2>\n<p>Look-ahead carry generator Capable of anticipating a carry across four binary adders or group of adders.<br \/>\nCascadable to perform full look-ahead across n-bit adders.<\/p>\n<pre>    +---+--+---+\r\n\/G1 |1  +--+ 16| VCC\r\n\/P1 |2       15| \/P2\r\n\/G0 |3       14| \/G2\r\n\/P0 |4   74  13| Cn\r\n\/G3 |5  182  12| Cn+X\r\n\/P3 |6       11| Cn+Y\r\n \/P |7       10| \/G\r\nGND |8        9| Cn+Z\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74183\"><\/a><\/p>\n<h2>74183<\/h2>\n<p>Dual full adder.<\/p>\n<pre>    +---+--+---+           +---+---+---*---+---+\r\n 1A |1  +--+ 14| VCC       | CI| A | B | S | CO|\r\n    |2       13| 2A        +===+===+===*===+===+\r\n 1B |3  74   12| 2B        | 0 | 0 | 0 | 0 | 0 |\r\n1CI |4  183  11| 2CI       | 0 | 0 | 1 | 1 | 0 |\r\n1CO |5       10| 2CO       | 0 | 1 | 0 | 1 | 0 |\r\n 1S |6        9|           | 0 | 1 | 1 | 0 | 1 |\r\nGND |7        8| 2S        | 1 | 0 | 0 | 1 | 0 |\r\n    +----------+           | 1 | 0 | 1 | 0 | 1 |\r\n                           | 1 | 1 | 0 | 0 | 1 |\r\n                           | 1 | 1 | 1 | 1 | 1 |\r\n                           +---+---+---*---+---+\r\n<\/pre>\n<p><a name=\"74190\"><\/a><\/p>\n<h2>74190<\/h2>\n<p>4-bit synchronous decade up\/down counter with load and both carry out and ripple clock outputs.<\/p>\n<pre>       +---+--+---+\r\n    P1 |1  +--+ 16| VCC\r\n    Q1 |2       15| P0\r\n    Q0 |3       14| CLK\r\n\/CLKEN |4   74  13| \/RCLK\r\n  D\/\/U |5  190  12| \/RCO\r\n    Q2 |6       11| \/LOAD\r\n    Q3 |7       10| P2\r\n   GND |8        9| P3\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74191\"><\/a><\/p>\n<h2>74191<\/h2>\n<p>4-bit synchronous binary up\/down counter with load and both carry out and ripple clock outputs.<\/p>\n<pre>       +---+--+---+\r\n    P1 |1  +--+ 16| VCC\r\n    Q1 |2       15| P0\r\n    Q0 |3       14| CLK\r\n\/CLKEN |4   74  13| \/RCLK\r\n  D\/\/U |5  191  12| \/RCO\r\n    Q2 |6       11| \/LOAD\r\n    Q3 |7       10| P2\r\n   GND |8        9| P3\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74192\"><\/a><\/p>\n<h2>74192<\/h2>\n<p>4-bit synchronous decade up\/down counter with asynchronous load and reset, and separate up and down clocks, carry and borrow outputs.<\/p>\n<pre>     +---+--+---+\r\n  P1 |1  +--+ 16| VCC\r\n  Q1 |2       15| P0\r\n  Q0 |3       14| RST\r\nDOWN |4   74  13| \/BORROW\r\n  UP |5  192  12| \/CARRY\r\n  Q2 |6       11| \/LOAD\r\n  Q3 |7       10| P2\r\n GND |8        9| P3\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74193\"><\/a><\/p>\n<h2>74193<\/h2>\n<p>4-bit synchronous binary up\/down counter with asynchronous load and reset, and separate up and down clocks. Carry and borrow outputs.<\/p>\n<pre>     +---+--+---+\r\n  P1 |1  +--+ 16| VCC\r\n  Q1 |2       15| P0\r\n  Q0 |3       14| RST\r\nDOWN |4   74  13| \/BORROW\r\n  UP |5  193  12| \/CARRY\r\n  Q2 |6       11| \/LOAD\r\n  Q3 |7       10| P2\r\n GND |8        9| P3\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74194\"><\/a><\/p>\n<h2>74194<\/h2>\n<p>4-bit bidirectional universal shift register with asynchronous reset.<\/p>\n<pre>     +---+--+---+            +---+---*---------------+\r\n\/RST |1  +--+ 16| VCC        | S1| S0| Function      |\r\n   D |2       15| Q0         +===+===*===============+\r\n  P0 |3       14| Q1         | 0 | 0 | Hold          |\r\n  P1 |4 40194 13| Q2         | 0 | 1 | Shift right   |\r\n  P2 |5 74194 12| Q3         | 1 | 0 | Shift left    |\r\n  P3 |6       11| CLK        | 1 | 1 | Parallel load |\r\n   L |7       10| S1         +---+---*---------------+\r\n GND |8        9| S0\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74195\"><\/a><\/p>\n<h2>74195<\/h2>\n<p>4-bit universal shift register with J-\/K inputs and asynchronous reset.<\/p>\n<pre>     +---+--+---+\r\n\/RST |1  +--+ 16| VCC\r\n   J |2       15| Q0\r\n  \/K |3       14| Q1\r\n  P0 |4   74  13| Q2\r\n  P1 |5  195  12| Q3\r\n  P2 |6       11| \/Q3\r\n  P3 |7       10| CLK\r\n GND |8        9| SH\/\/LD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74196\"><\/a><\/p>\n<h2>74196<\/h2>\n<p>4-bit asynchronous decade counter with \/2 and \/5 sections, load and reset.<\/p>\n<pre>      +---+--+---+\r\n\/LOAD |1  +--+ 14| VCC\r\n   Q2 |2       13| \/RST\r\n   P2 |3   74  12| Q3\r\n   P0 |4  196  11| P3\r\n   Q0 |5       10| P1\r\n\/CLK1 |6        9| Q1\r\n  GND |7        8| \/CLK0\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74197\"><\/a><\/p>\n<h2>74197<\/h2>\n<p>4-bit asynchronous binary counter with \/2 and \/8 sections, load and reset.<\/p>\n<pre>      +---+--+---+\r\n\/LOAD |1  +--+ 14| VCC\r\n   Q2 |2       13| \/RST\r\n   P2 |3   74  12| Q3\r\n   P0 |4  197  11| P3\r\n   Q0 |5       10| P1\r\n\/CLK1 |6        9| Q1\r\n  GND |7        8| \/CLK0\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74198\"><\/a><\/p>\n<h2>74198<\/h2>\n<p>8-bit bidirectional universal shift register with asynchronous reset.<\/p>\n<pre>    +---+--+---+\r\n S0 |1  +--+ 24| VCC\r\n  D |2       23| S1\r\n P0 |3       22| Q7\r\n Y0 |4       21| P7\r\n P1 |5       20| Y7\r\n Y1 |6   74  19| P6\r\n P2 |7  198  18| Y6\r\n Y2 |8       17| P5\r\n P3 |9       16| Y5\r\n Y3 |10      15| P4\r\nCLK |11      14| Y4\r\nGND |12      13| \/RST\r\n    +----------+<\/pre>\n<p>&nbsp;<\/p>\n<h2>74203<\/h2>\n<p>6-line inverting clock driver.<\/p>\n<pre>    +---+--+---+\r\n 1Y |1  +--+ 20| 1A\r\n 2Y |2       19| 2A\r\n 3Y |3       18| 3A\r\nGND |4       17|\r\nGND |5   74  16| VCC\r\nGND |6  203  15| VCC\r\nGND |7       14|\r\n 4Y |8       13| 4A\r\n 5Y |9       12| 5A\r\n 6Y |10      11| 6A\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74204\"><\/a><\/p>\n<h2>74204<\/h2>\n<p>6-line inverting clock driver.<\/p>\n<pre>    +---+--+---+\r\n 1Y |1  +--+ 20| 1A\r\n 2Y |2       19| 2A\r\n 3Y |3       18| 3A\r\nGND |4       17|\r\nGND |5   74  16| VCC\r\nGND |6  204  15| VCC\r\nGND |7       14|\r\n 4Y |8       13| 4A\r\n 5Y |9       12| 5A\r\n 6Y |10      11| 6A\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74208\"><\/a><\/p>\n<h2>74208<\/h2>\n<p>Dual 3-state 1-line to 4-line noninverting clock driver.<\/p>\n<pre>    +---+--+---+\r\n1Y2 |1  +--+ 20| 1Y1\r\n1Y3 |2       19| 1A\r\n1Y4 |3       18| \/1OE1\r\nGND |4       17| \/1OE2\r\nGND |5   74  16| VCC\r\nGND |6  208  15| VCC\r\nGND |7       14| 2A\r\n2Y1 |8       13| \/2OE1\r\n2Y2 |9       12| \/2OE2\r\n2Y3 |10      11| 2Y4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74209\"><\/a><\/p>\n<h2>74209<\/h2>\n<p>Dual 3-state 1-line to 4-line noninverting clock driver.<\/p>\n<pre>    +---+--+---+\r\n1Y2 |1  +--+ 20| 1Y1\r\n1Y3 |2       19| 1A\r\n1Y4 |3       18| \/1OE1\r\nGND |4       17| \/1OE2\r\nGND |5   74  16| VCC\r\nGND |6  209  15| VCC\r\nGND |7       14| 2A\r\n2Y1 |8       13| \/2OE1\r\n2Y2 |9       12| \/2OE2\r\n2Y3 |10      11| 2Y4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74221\"><\/a><\/p>\n<h2>74221<\/h2>\n<p>Dual monostable multivibrators with Schmitt-trigger inputs.<\/p>\n<pre>       +---+--+---+\r\n  \/1TR |1  +--+ 16| VCC\r\n   1TR |2       15| 1RCext\r\n \/1RST |3       14| 1Cext\r\n   \/1Q |4   74  13| 1Q\r\n    2Q |5  221  12| \/2Q\r\n 2Cext |6       11| \/2RST\r\n2RCext |7       10| 2TR\r\n   GND |8        9| \/2TR\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74237\"><\/a><\/p>\n<h2>74237<\/h2>\n<p>1-of-8 noninverting decoder\/demultiplexer with address latches.<\/p>\n<pre>     +---+--+---+\r\n  S0 |1  +--+ 16| VCC\r\n  S1 |2       15| Y0\r\n  S2 |3       14| Y1\r\n \/LE |4   74  13| Y2\r\n\/EN2 |5  237  12| Y3\r\n EN1 |6       11| Y4\r\n  Y7 |7       10| Y5\r\n GND |8        9| Y6\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74238\"><\/a><\/p>\n<h2>74238<\/h2>\n<p>1-of-8 noninverting decoder\/demultiplexer.<\/p>\n<pre>     +---+--+---+            +---+----+----+---+---+---*---+---+---+---+\r\n  S0 |1  +--+ 16| VCC        |EN1|\/EN2|\/EN3| S2| S1| S0|\/Y0|\/Y1|...|\/Y7|\r\n  S1 |2       15| Y0         +===+====+====+===+===+===*===+===+===+===+\r\n  S2 |3       14| Y1         | 0 | X  |  X | X | X | X | 0 | 0 | 0 | 0 |\r\n\/EN3 |4   74  13| Y2         | 1 | 1  |  X | X | X | X | 0 | 0 | 0 | 0 |\r\n\/EN2 |5  238  12| Y3         | 1 | 0  |  1 | X | X | X | 0 | 0 | 0 | 0 |\r\n EN1 |6       11| Y4         | 1 | 0  |  0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |\r\n  Y7 |7       10| Y5         | 1 | 0  |  0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |\r\n GND |8        9| Y6         | 1 | 0  |  0 | . | . | . | 0 | 0 | . | 0 |\r\n     +----------+            | 1 | 0  |  0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |\r\n                             +---+----+----+---+---+---*---+---+---+---+\r\n<\/pre>\n<p><a name=\"74239\"><\/a><\/p>\n<h2>74239<\/h2>\n<p>Dual 1-of-4 noninverting decoder\/demultiplexer.<\/p>\n<pre>     +---+--+---+            +---+---+---*---+---+---+---+\r\n\/1EN |1  +--+ 16| VCC        |\/EN| S1| S0| Y0| Y1| Y2| Y3|\r\n 1S0 |2       15| \/2EN       +===+===+===*===+===+===+===+\r\n 1S1 |3       14| 2S0        | 1 | X | X | 0 | 0 | 0 | 0 |\r\n 1Y0 |4   74  13| 2S1        | 0 | 0 | 0 | 1 | 0 | 0 | 0 |\r\n 1Y1 |5  239  12| 2Y0        | 0 | 0 | 1 | 0 | 1 | 0 | 0 |\r\n 1Y2 |6       11| 2Y1        | 0 | 1 | 0 | 0 | 0 | 1 | 0 |\r\n 1Y3 |7       10| 2Y2        | 0 | 1 | 1 | 0 | 0 | 0 | 1 |\r\n GND |8        9| 2Y3        +---+---+---*---+---+---+---+\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74240\"><\/a><\/p>\n<h2>74240<\/h2>\n<p>Dual 4-bit 3-state inverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+\r\n\/1OE |1  +--+ 20| VCC\r\n 1A1 |2       19| \/2OE\r\n\/2Y4 |3       18| \/1Y1\r\n 1A2 |4       17| 2A4\r\n\/2Y3 |5  74   16| \/1Y2\r\n 1A3 |6  240  15| 2A3\r\n\/2Y2 |7       14| \/1Y3\r\n 1A4 |8       13| 2A2\r\n\/2Y1 |9       12| \/1Y4\r\n GND |10      11| 2A1\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74241\"><\/a><\/p>\n<h2>74241<\/h2>\n<p>Dual 4-bit 3-state noninverting buffer\/line driver.<br \/>\nOne active low, one active high output enable.<\/p>\n<pre>     +---+--+---+\r\n\/1OE |1  +--+ 20| VCC\r\n 1A4 |2       19| 2OE\r\n 2Y1 |3       18| 1Y1\r\n 1A3 |4       17| 2A4\r\n 2Y2 |5  74   16| 1Y2\r\n 1A2 |6  241  15| 2A3\r\n 2Y3 |7       14| 1Y3\r\n 1A1 |8       13| 2A2\r\n 2Y4 |9       12| 1Y4\r\n GND |10      11| 2A1\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74242\"><\/a><\/p>\n<h2>74242<\/h2>\n<p>4-bit 3-state inverting bus transceiver.<br \/>\nTwo enable pins control output enables, one active high and one active low.<\/p>\n<pre>     +---+--+---+\r\n\/GAB |1  +--+ 14| VCC\r\n     |2       13| GBA\r\n  A1 |3  74   12|\r\n  A2 |4  242  11| B1\r\n  A3 |5       10| B2\r\n  A4 |6        9| B3\r\n GND |7        8| B4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74243\"><\/a><\/p>\n<h2>74243<\/h2>\n<p>4-bit 3-state noninverting bus transceiver.<br \/>\nTwo enable pins control output enables, one active high and one active low.<\/p>\n<pre>     +---+--+---+\r\n\/GAB |1  +--+ 14| VCC\r\n     |2       13| GBA\r\n  A1 |3  74   12|\r\n  A2 |4  243  11| B1\r\n  A3 |5       10| B2\r\n  A4 |6        9| B3\r\n GND |7        8| B4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74244\"><\/a><\/p>\n<h2>74244<\/h2>\n<p>Dual 4-bit 3-state noninverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+\r\n\/1OE |1  +--+ 20| VCC\r\n 1A1 |2       19| \/2OE\r\n 2Y4 |3       18| 1Y1\r\n 1A2 |4       17| 2A4\r\n 2Y3 |5  74   16| 1Y2\r\n 1A3 |6  244  15| 2A3\r\n 2Y2 |7       14| 1Y3\r\n 1A4 |8       13| 2A2\r\n 2Y1 |9       12| 1Y4\r\n GND |10      11| 2A1\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74245\"><\/a><\/p>\n<h2>74245<\/h2>\n<p>8-bit 3-state noninverting bus transceiver.<br \/>\nEnable and direction pins control output enables.<\/p>\n<pre>    +---+--+---+             +---+---*---+---+\r\nDIR |1  +--+ 20| VCC         |\/EN|DIR| A | B |\r\n A1 |2       19| \/EN         +===+===*===+===+\r\n A2 |3       18| B1          | 1 | X | Z | Z |\r\n A3 |4       17| B2          | 0 | 0 | B | Z |\r\n A4 |5  74   16| B3          | 0 | 1 | Z | A |\r\n A5 |6  245  15| B4          +---+---*---+---+\r\n A6 |7       14| B5\r\n A7 |8       13| B6\r\n A8 |9       12| B7\r\nGND |10      11| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74247\"><\/a><\/p>\n<h2>74247<\/h2>\n<p>Open-collector BCD to 7-segment decoder\/common-anode LED driver with ripple blank input and output.<\/p>\n<pre>     +---+--+---+\r\n  A1 |1  +--+ 16| VCC\r\n  A2 |2       15| \/YF\r\n \/LT |3       14| \/YG\r\n\/RBO |4  74   13| \/YA\r\n\/RBI |5  247  12| \/YB\r\n  A3 |6       11| \/YC\r\n  A0 |7       10| \/YD\r\n GND |8        9| \/YE\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74248\"><\/a><\/p>\n<h2>74248<\/h2>\n<p>BCD to 7-segment decoder\/common-cathode LED driver with ripple blank input and output.<\/p>\n<pre>     +---+--+---+\r\n  A1 |1  +--+ 16| VCC\r\n  A2 |2       15| YF\r\n \/LT |3       14| YG\r\n\/RBO |4  74   13| YA\r\n\/RBI |5  248  12| YB\r\n  A3 |6       11| YC\r\n  A0 |7       10| YD\r\n GND |8        9| YE\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74251\"><\/a><\/p>\n<h2>74251<\/h2>\n<p>8-to-1 line 3-state data selector\/multiplexer with complementary outputs.<\/p>\n<pre>    +---+--+---+\r\n A3 |1  +--+ 16| VCC\r\n A2 |2       15| A4\r\n A1 |3       14| A5\r\n A0 |4   74  13| A6\r\n  Y |5  251  12| A7\r\n \/Y |6       11| S0\r\n\/EN |7       10| S1\r\nGND |8        9| S2\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74253\"><\/a><\/p>\n<h2>74253<\/h2>\n<p>8-to-2 line 3-state noninverting data selector\/multiplexer.<\/p>\n<pre>     +---+--+---+\r\n\/1EN |1  +--+ 16| VCC\r\n  S1 |2       15| \/2EN\r\n 1A3 |3       14| S0\r\n 1A2 |4   74  13| 2A3\r\n 1A1 |5  253  12| 2A2\r\n 1A0 |6       11| 2A1\r\n  1Y |7       10| 2A0\r\n GND |8        9| 2Y\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74256\"><\/a><\/p>\n<h2>74256<\/h2>\n<p>2-of-8 addressable latch with reset and enable.<\/p>\n<pre>     +---+--+---+            +---+----*--------------------+\r\n  S0 |1  +--+ 16| VCC        |\/EN|\/RST| Function           |\r\n  S1 |2       15| \/RST       +===+====*====================+\r\n  1D |3       14| \/EN        | 0 |  0 | 2-of-8 demultiplex |\r\n 1Q0 |4  74   13| 2D         | 0 |  1 | addressable latch  |\r\n 1Q1 |5  256  12| 2Q3        | 1 |  0 | reset              |\r\n 1Q2 |6       11| 2Q2        | 1 |  1 | hold               |\r\n 1Q3 |7       10| 2Q1        +---+----*--------------------+\r\n GND |8        9| 2Q0\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74257\"><\/a><\/p>\n<h2>74257<\/h2>\n<p>8-to-4 line 3-state noninverting data selector\/multiplexer.<\/p>\n<pre>    +---+--+---+\r\n  S |1  +--+ 16| VCC\r\n1A0 |2       15| \/EN\r\n1A1 |3       14| 4A0\r\n 1Y |4   74  13| 4A1\r\n2A0 |5  257  12| 4Y\r\n2A1 |6       11| 3A0\r\n 2Y |7       10| 3A1\r\nGND |8        9| 3Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74258\"><\/a><\/p>\n<h2>74258<\/h2>\n<p>8-to-4 line 3-state inverting data selector\/multiplexer.<\/p>\n<pre>    +---+--+---+\r\n  S |1  +--+ 16| VCC\r\n1A0 |2       15| \/EN\r\n1A1 |3       14| 4A0\r\n\/1Y |4   74  13| 4A1\r\n2A0 |5  258  12| \/4Y\r\n2A1 |6       11| 3A0\r\n\/2Y |7       10| 3A1\r\nGND |8        9| \/3Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74259\"><\/a><\/p>\n<h2>74259<\/h2>\n<p>1-of-8 addressable latch with reset.<\/p>\n<pre>    +---+--+---+             +---+----*--------------------+\r\n S0 |1  +--+ 16| VCC         |\/EN|\/RST| Function           |\r\n S1 |2       15| \/RST        +===+====*====================+\r\n S2 |3       14| \/EN         | 0 |  0 | 1-of-8 demultiplex |\r\n Q0 |4   74  13| D           | 0 |  1 | addressable latch  |\r\n Q1 |5  259  12| Q7          | 1 |  0 | reset              |\r\n Q2 |6       11| Q6          | 1 |  1 | hold               |\r\n Q3 |7       10| Q5          +---+----*--------------------+\r\nGND |8        9| Q4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74260\"><\/a><\/p>\n<h2>74260<\/h2>\n<p>Dual 5-input NOR gates.<\/p>\n<pre>    +---+--+---+                 ___________\r\n 1A |1  +--+ 14| VCC         Y = (A+B+C+D+E)\r\n 1B |2       13| 2D\r\n 1E |3   74  12| 2C\r\n 1C |4  260  11| 2E\r\n 1D |5       10| 2B\r\n\/1Y |6        9| 2A\r\nGND |7        8| \/2Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74265\"><\/a><\/p>\n<h2>74265<\/h2>\n<p>Dual buffer\/inverter plus dual AND\/NAND gates.<\/p>\n<pre>    +---+--+---+\r\n 1A |1  +--+ 16| VCC         1Y=1A\r\n 1Y |2       15| 4A\r\n\/1Y |3       14| 4Y          2Y=2A.2B\r\n 2A |4   74  13| \/4Y\r\n 2B |5  265  12| 3B          3Y=3A.3B\r\n 2Y |6       11| 3A\r\n\/2Y |7       10| 3Y          4Y=4A\r\nGND |8        9| \/3Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74266\"><\/a><\/p>\n<h2>74266<\/h2>\n<p>Quad 2-input open-collector XNOR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+          _     _ _\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |     Y = A$B = (A.B)+(A.B)\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3  74   12| 4A          | 0 | 0 | Z |\r\n 2A |4  266  11| \/4Y         | 0 | 1 | 0 |\r\n 2B |5       10| 3B          | 1 | 0 | 0 |\r\n\/2Y |6        9| 3A          | 1 | 1 | Z |\r\nGND |7        8| \/3Y         +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74273\"><\/a><\/p>\n<h2>74273<\/h2>\n<p>8-bit 3-state D flip-flop with reset.<\/p>\n<pre>     +---+--+---+            +----+---+---*---+\r\n\/RST |1  +--+ 20| VCC        |\/RST|CLK| D | Q |\r\n  1Q |2       19| 8Q         +====+===+===*===+\r\n  1D |3       18| 8D         |  0 | X | X | 0 |\r\n  2D |4       17| 7D         |  1 | \/ | 0 | 0 |\r\n  2Q |5   74  16| 7Q         |  1 | \/ | 1 | 1 |\r\n  3Q |6  273  15| 6Q         +----+---+---*---+\r\n  3D |7       14| 6D\r\n  4D |8       13| 5D\r\n  4Q |9       12| 5Q\r\n GND |10      11| CLK\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74276\"><\/a><\/p>\n<h2>74276<\/h2>\n<p>Quad J-K and J-\/K flip-flops with common set and reset.<\/p>\n<pre>      +---+--+---+\r\n \/RST |1  +--+ 20| VCC\r\n   1J |2       19| 4J\r\n\/1CLK |3       18| \/4CLK\r\n  \/1K |4       17| 4K\r\n   1Q |5   74  16| 4Q\r\n   2Q |6  276  15| 3Q\r\n  \/2K |7       14| \/3K\r\n\/2CLK |8       13| \/3CLK\r\n   2J |9       12| 3J\r\n  GND |10      11| \/SET\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74279\"><\/a><\/p>\n<h2>74279<\/h2>\n<p>Quad \/S-\/R latches.<\/p>\n<pre>     +---+--+---+\r\n \/1R |1  +--+ 16| VCC\r\n\/1S1 |2       15| \/4S\r\n\/1S2 |3       14| \/4R\r\n  1Q |4   74  13| 4Q\r\n \/2R |5  279  12| \/3S2\r\n \/2S |6       11| \/3S1\r\n  2Q |7       10| \/3R\r\n GND |8        9| 3Q\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74280\"><\/a><\/p>\n<h2>74280<\/h2>\n<p>9-bit odd\/even parity generator\/checker.<\/p>\n<pre>      +---+--+---+\r\n   A0 |1  +--+ 14| VCC\r\n   A1 |2       13| A8\r\n      |3   74  12| A7\r\n   A2 |4  280  11| A6\r\n EVEN |5       10| A5\r\n  ODD |6        9| A4\r\n  GND |7        8| A3\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74283\"><\/a><\/p>\n<h2>74283<\/h2>\n<p>4-bit binary full adder with fast carry.<\/p>\n<pre>    +---+--+---+\r\n S2 |1  +--+ 16| VCC         S=A+B+CIN\r\n B2 |2       15| B3\r\n A2 |3       14| A3\r\n S1 |4   74  13| S3\r\n A1 |5  283  12| A4\r\n B1 |6       11| B4\r\nCIN |7       10| S4\r\nGND |8        9| COUT\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74285\"><\/a><\/p>\n<h2>74285<\/h2>\n<p>4-bit binary multiplier with open-collector outputs.<\/p>\n<pre>    +---+--+---+\r\n 2C |1  +--+ 16| VCC\r\n 2B |2       15| 2D\r\n 2A |3       14| \/GA\r\n 1D |4   74  13| \/GB\r\n 1A |5  285  12| Y0\r\n 1B |6       11| Y1\r\n 1C |7       10| Y2\r\nGND |8        9| Y3\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74286\"><\/a><\/p>\n<h2>74286<\/h2>\n<p>9-bit odd\/even parity generator\/checker with bus driver parity I\/O port.<\/p>\n<pre>      +---+--+---+\r\n   A0 |1  +--+ 14| VCC\r\n   A1 |2       13| A8\r\n\/XMIT |3   74  12| A7\r\n   A2 |4  286  11| A6\r\nERROR |5       10| A5\r\n PI\/O |6        9| A4\r\n  GND |7        8| A3\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74290\"><\/a><\/p>\n<h2>74290<\/h2>\n<p>4-bit asynchronous decade counter with \/2 and \/5 sections, set(9) and reset.<\/p>\n<pre>     +---+--+---+\r\nSET1 |1  +--+ 14| VCC\r\n     |2       13| RST2\r\nSET2 |3   74  12| RST1\r\n  Q2 |4  290  11| \/CLK1\r\n  Q1 |5       10| \/CLK0\r\n     |6        9| Q0\r\n GND |7        8| Q3\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74292\"><\/a><\/p>\n<h2>74292<\/h2>\n<p>15-bit programmable frequency divider\/digital timer.<br \/>\nDigitally programmable from 2^2 to 2^15.<\/p>\n<pre>     +---+--+---+\r\n  S1 |1  +--+ 16| VCC\r\n  S4 |2       15| S2\r\n TP1 |3       14| S3\r\nCLK1 |4  74   13| TP3\r\nCLK2 |5  292  12|\r\n TP2 |6       11| \/RST\r\n   Q |7       10| S0\r\n GND |8        9|\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74293\"><\/a><\/p>\n<h2>74293<\/h2>\n<p>4-bit asynchronous binary counter with \/2 and \/8 sections and reset.<\/p>\n<pre>     +---+--+---+\r\n     |1  +--+ 14| VCC\r\n     |2       13| RST2\r\n     |3       12| RST1\r\n  Q2 |4  74   11| \/CLK1\r\n  Q1 |5  293  10| \/CLK0\r\n     |6        9| Q0\r\n GND |7        8| Q3\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74294\"><\/a><\/p>\n<h2>74294<\/h2>\n<p>15-bit programmable frequency divider\/digital timer.<br \/>\nDigitally programmable from 2^2 to 2^15.<\/p>\n<pre>     +---+--+---+\r\n  S1 |1  +--+ 16| VCC\r\n  S0 |2       15| S2\r\n  TP |3       14| S3\r\nCLK1 |4  74   13|\r\nCLK2 |5  294  12|\r\n     |6       11| \/RST\r\n   Q |7       10|\r\n GND |8        9|\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74295\"><\/a><\/p>\n<h2>74295<\/h2>\n<p>4-bit 3-state negative-edge-triggered universal shift register.<\/p>\n<pre>       +---+--+---+\r\n     D |1  +--+ 14| VCC\r\n    P0 |2       13| Y0\r\n    P1 |3       12| Y1\r\n    P2 |4  74   11| Y2\r\n    P3 |5  295  10| Y3\r\nLD\/\/SH |6        9| \/CLK\r\n   GND |7        8| OE\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74297\"><\/a><\/p>\n<h2>74297<\/h2>\n<p>Digital phase-locked loop with 4-bit counter.<\/p>\n<pre>      +---+--+---+\r\n   D1 |1  +--+ 16| VCC\r\n   D0 |2       15| D2\r\n   EN |3       14| D3\r\n  KCP |4  74   13| PA2\r\n I\/\/D |5  297  12| ECPD\r\n D\/\/U |6       11| XORPD\r\nIDout |7       10| PB\r\n  GND |8        9| PA1\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74298\"><\/a><\/p>\n<h2>74298<\/h2>\n<p>8-to-4 line noninverting data selector\/multiplexer with output registers.<\/p>\n<pre>    +---+--+---+\r\n2A1 |1  +--+ 16| VCC\r\n2A0 |2       15| 1Q\r\n1A0 |3       14| 2Q\r\n1A1 |4   74  13| 3Q\r\n3A1 |5  298  12| 4Q\r\n4A1 |6       11| CLK\r\n4A0 |7       10| S\r\nGND |8        9| 3A0\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74299\"><\/a><\/p>\n<h2>74299<\/h2>\n<p>8-bit 3-state bidirectional universal shift register with asynchronous reset and with separate shift left and shift right serial inputs. Multiplexed parallel I\/O.<\/p>\n<pre>     +---+--+---+\r\n  S0 |1  +--+ 20| VCC\r\n\/OE1 |2       19| S1\r\n\/OE2 |3       18| D\r\n  P6 |4       17| Q7\r\n  P4 |5   74  16| P7\r\n  P2 |6  299  15| P5\r\n  P0 |7       14| P3\r\n  Q0 |8       13| P1\r\n\/RST |9       12| CLK\r\n GND |10      11| L\r\n     +----------+<\/pre>\n<p>&nbsp;<\/p>\n<h2>74303<\/h2>\n<p>8-line inverting\/noninverting divide by 2 clock driver.<br \/>\nSix outputs in phase with CLK, two out of phase.<\/p>\n<pre>    +---+--+---+\r\n Q3 |1  +--+ 16| Q2\r\n Q4 |2       15| Q1\r\nGND |3       14| \/RST\r\nGND |4   74  13| VCC\r\nGND |5  303  12| VCC\r\n Q5 |6       11| CLK\r\n Q6 |7       10| \/PRE\r\n\/Q7 |8        9| \/Q8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74304\"><\/a><\/p>\n<h2>74304<\/h2>\n<p>8-line noninverting divide by 2 clock driver.<\/p>\n<pre>    +---+--+---+\r\n Q3 |1  +--+ 16| Q2\r\n Q4 |2       15| Q1\r\nGND |3       14| \/RST\r\nGND |4   74  13| VCC\r\nGND |5  304  12| VCC\r\n Q5 |6       11| CLK\r\n Q6 |7       10| \/PRE\r\n Q7 |8        9| Q8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74305\"><\/a><\/p>\n<h2>74305<\/h2>\n<p>8-line inverting\/noninverting divide by 2 clock driver.<br \/>\nFour outputs in phase with CLK, four out of phase.<\/p>\n<pre>    +---+--+---+\r\n Q3 |1  +--+ 16| Q2\r\n Q4 |2       15| Q1\r\nGND |3       14| \/RST\r\nGND |4   74  13| VCC\r\nGND |5  305  12| VCC\r\n\/Q5 |6       11| CLK\r\n\/Q6 |7       10| \/PRE\r\n\/Q7 |8        9| \/Q8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74306\"><\/a><\/p>\n<h2>74306<\/h2>\n<p>2-bit 3-state noninverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+            +---+---*---+\r\n\/1OE |1  +--+  8| 1Y         | A |\/OE| Y |\r\n  1A |2   74   7| VCC        +===+===*===+\r\n GND |3  306   6| 1A         | 0 | 0 | 0 |\r\n\/2OE |4        5| 2Y         | 1 | 0 | 1 |\r\n     +----------+            | X | 1 | Z |\r\n                             +---+---*---+\r\n<\/pre>\n<p><a name=\"74322\"><\/a><\/p>\n<h2>74322<\/h2>\n<p>8-bit 3-state shift register with with sign extension and selectable serial inputs. Multiplexed parallel I\/O.<\/p>\n<pre>       +---+--+---+\r\n   \/OE |1  +--+ 20| VCC\r\nSH\/\/LD |2       19| E\/\/D\r\n     D |3       18| \/SEXT\r\n    P0 |4       17| E\r\n    P2 |5   74  16| P1\r\n    P4 |6  322  15| P3\r\n    P6 |7       14| P5\r\n   \/OE |8       13| P7\r\n  \/RST |9       12| Q7\r\n   GND |10      11| CLK\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74323\"><\/a><\/p>\n<h2>74323<\/h2>\n<p>8-bit 3-state bidirectional universal shift register with reset and multiplexed parallel I\/O.<\/p>\n<pre>     +---+--+---+\r\n  S0 |1  +--+ 20| VCC\r\n\/OE1 |2       19| S1\r\n\/OE2 |3       18| D\r\n  P6 |4       17| Q7\r\n  P4 |5   74  16| P7\r\n  P2 |6  323  15| P5\r\n  P0 |7       14| P3\r\n  Q0 |8       13| P1\r\n\/RST |9       12| CLK\r\n GND |10      11| L\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74328\"><\/a><\/p>\n<h2>74328<\/h2>\n<p>6-line selectable phase clock driver.<\/p>\n<pre>    +---+--+---+\r\nGND |1  +--+ 16| 1Y1\r\n1Y2 |2       15| SEL1\r\n2Y1 |3       14| VCC\r\nGND |4   74  13| SEL2\r\n2Y2 |5  328  12| A\r\n3Y1 |6       11| VCC\r\nGND |7       10| SEL3\r\n4Y1 |8        9| SEL4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74329\"><\/a><\/p>\n<h2>74329<\/h2>\n<p>6-line selectable phase clock driver.<\/p>\n<pre>    +---+--+---+\r\nGND |1  +--+ 16| 1Y1\r\n1Y2 |2       15| SEL1\r\n2Y1 |3       14| VCC\r\nGND |4   74  13| SEL2\r\n2Y2 |5  329  12| A\r\n3Y1 |6       11| VCC\r\nGND |7       10| SEL3\r\n4Y1 |8        9| SEL4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74330\"><\/a><\/p>\n<h2>74330<\/h2>\n<p>Dual 1-line to 3-line noninverting clock driver and 1-line to 4-line noninverting divide by 2 clock driver.<\/p>\n<pre>     +---+--+---+\r\n GND |1  +--+ 24| OEQ\r\n  Q1 |2       23| Q3\r\n  Q2 |3       22| CLKQ\r\n GND |4       21| VCC\r\n  X1 |5       20| RST\r\n OEX |6   74  19| X3\r\nCLKX |7  330  18| GND\r\n  X2 |8       17| X4\r\n GND |9       16| VCC\r\n  Y1 |10      15| OEY\r\n  Y2 |11      14| Y3\r\n GND |12      13| CLKY\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74337\"><\/a><\/p>\n<h2>74337<\/h2>\n<p>8-line 3-state noninverting clock driver with divide by 2 output on 4 lines.<\/p>\n<pre>     +---+--+---+\r\n  Y3 |1  +--+ 20| Y2\r\n GND |2       19| GND\r\n  Y4 |3       18| Y1\r\n VCC |4       17| VCC\r\n \/OE |5   74  16| CLK\r\n\/RST |6  337  15| GND\r\n VCC |7       14| VCC\r\n  Q1 |8       13| Q4\r\n GND |9       12| GND\r\n  Q2 |10      11| Q3\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74338\"><\/a><\/p>\n<h2>74338<\/h2>\n<p>6-line noninverting clock driver with divide by 2 and PLL.<br \/>\nFour outputs toggle at the clock, one at one-half, one at double speed.<\/p>\n<pre>    +---+--+---+\r\nGND |1  +--+ 20| \/OE\r\n Y1 |2       19| VCC\r\nGND |3       18| DF\r\n Y2 |4       17| VCC\r\nGND |5   74  16| CLKIN\r\nGND |6  338  15| GND\r\n Y3 |7       14| HF\r\nGND |8       13| VCC\r\n Y4 |9       12| \/RST\r\nGND |10      11| VCC\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74339\"><\/a><\/p>\n<h2>74339<\/h2>\n<p>8-line 3-state noninverting clock driver with divide by 2 output on 4 lines.<\/p>\n<pre>     +---+--+---+\r\n  Y3 |1  +--+ 20| Y2\r\n GND |2       19| GND\r\n  Y4 |3       18| Y1\r\n VCC |4       17| VCC\r\n \/OE |5   74  16| CLK\r\n\/RST |6  339  15| GND\r\n VCC |7       14| VCC\r\n  Q1 |8       13| Q4\r\n GND |9       12| GND\r\n  Q2 |10      11| Q3\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74340\"><\/a><\/p>\n<h2>74340<\/h2>\n<p>8-line inverting clock driver.<\/p>\n<pre>    +---+--+---+\r\nVCC |1  +--+ 20| VCC\r\n E1 |2       19| Q1\r\n E2 |3       18| Q2\r\n IN |4       17| GND\r\n P0 |5   74  16| Q3\r\n P1 |6  340  15| Q4\r\nVCC |7       14| GND\r\n Q8 |8       13| Q5\r\n Q7 |9       12| Q6\r\nGND |10      11| GND\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74348\"><\/a><\/p>\n<h2>74348<\/h2>\n<p>8-to-3 line 3-state inverting priority encoder with cascade inputs.<\/p>\n<pre>    +---+--+---+\r\n\/A4 |1  +--+ 16| VCC\r\n\/A5 |2       15| \/EO\r\n\/A6 |3       14| \/GS\r\n\/A7 |4   74  13| \/A3\r\n\/EI |5  348  12| \/A2\r\n Y2 |6       11| \/A1\r\n Y1 |7       10| \/A0\r\nGND |8        9| Y0\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74352\"><\/a><\/p>\n<h2>74352<\/h2>\n<p>8-to-2 line inverting data selector\/multiplexer with separate enables.<\/p>\n<pre>     +---+--+---+\r\n\/1EN |1  +--+ 16| VCC\r\n  S1 |2       15| \/2EN\r\n 1A3 |3       14| S0\r\n 1A2 |4   74  13| 2A3\r\n 1A1 |5  352  12| 2A2\r\n 1A0 |6       11| 2A1\r\n  1Y |7       10| 2A0\r\n GND |8        9| 2Y\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74353\"><\/a><\/p>\n<h2>74353<\/h2>\n<p>8-to-2 line 3-state inverting data selector\/multiplexer.<\/p>\n<pre>     +---+--+---+\r\n\/1EN |1  +--+ 16| VCC\r\n  S1 |2       15| \/2EN\r\n 1A3 |3       14| S0\r\n 1A2 |4   74  13| 2A3\r\n 1A1 |5  353  12| 2A2\r\n 1A0 |6       11| 2A1\r\n \/1Y |7       10| 2A0\r\n GND |8        9| \/2Y\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74354\"><\/a><\/p>\n<h2>74354<\/h2>\n<p>8-to-1 line 3-state data selector\/multiplexer with address and data latches and complementary outputs.<\/p>\n<pre>    +---+--+---+\r\n A7 |1  +--+ 20| VCC\r\n A6 |2       19| Y\r\n A5 |3       18| \/Y\r\n A4 |4       17| OE3\r\n A3 |5  74   16| \/OE2\r\n A2 |6  354  15| \/OE1\r\n A1 |7       14| A0\r\n A0 |8       13| A1\r\nDLE |9       12| A2\r\nGND |10      11| ALE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74356\"><\/a><\/p>\n<h2>74356<\/h2>\n<p>8-to-1 line 3-state data selector\/multiplexer with address latch and data register and complementary outputs.<\/p>\n<pre>    +---+--+---+\r\n A7 |1  +--+ 20| VCC\r\n A6 |2       19| Y\r\n A5 |3       18| \/Y\r\n A4 |4       17| OE3\r\n A3 |5  74   16| \/OE2\r\n A2 |6  356  15| \/OE1\r\n A1 |7       14| A0\r\n A0 |8       13| A1\r\nDLE |9       12| A2\r\nGND |10      11| ALE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74365\"><\/a><\/p>\n<h2>74365<\/h2>\n<p>6-bit 3-state noninverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+            +---+---*---+\r\n\/OE1 |1  +--+ 16| VCC        |\/OE| A | Y |\r\n  A1 |2       15| \/OE2       +===+===*===+\r\n  Y1 |3       14| A6         | 1 | X | Z |\r\n  A2 |4   74  13| Y6         | 0 | 0 | 0 |\r\n  Y2 |5  365  12| A5         | 0 | 1 | 1 |\r\n  A3 |6       11| Y5         +---+---*---+\r\n  Y3 |7       10| A4\r\n GND |8        9| Y4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74366\"><\/a><\/p>\n<h2>74366<\/h2>\n<p>6-bit 3-state inverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+            +---+---*---+\r\n\/OE1 |1  +--+ 16| VCC        |\/OE| A |\/Y |\r\n  A1 |2       15| \/OE2       +===+===*===+\r\n \/Y1 |3       14| A6         | 1 | X | Z |\r\n  A2 |4   74  13| \/Y6        | 0 | 0 | 1 |\r\n \/Y2 |5  366  12| A5         | 0 | 1 | 0 |\r\n  A3 |6       11| \/Y5        +---+---*---+\r\n \/Y3 |7       10| A4\r\n GND |8        9| \/Y4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74367\"><\/a><\/p>\n<h2>74367<\/h2>\n<p>2\/4-bit 3-state noninverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+            +---+---*---+\r\n\/1OE |1  +--+ 16| VCC        |\/OE| A | Y |\r\n 1A1 |2       15| \/2OE       +===+===*===+\r\n 1Y1 |3       14| 2A2        | 1 | X | Z |\r\n 1A2 |4   74  13| 2Y2        | 0 | 0 | 0 |\r\n 1Y2 |5  367  12| 2A1        | 0 | 1 | 1 |\r\n 1A3 |6       11| 2Y1        +---+---*---+\r\n 1Y3 |7       10| 1A4\r\n GND |8        9| 1Y4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74368\"><\/a><\/p>\n<h2>74368<\/h2>\n<p>2\/4-bit 3-state inverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+            +---+---*---+\r\n\/1OE |1  +--+ 16| VCC        |\/OE| A |\/Y |\r\n 1A1 |2       15| \/2OE       +===+===*===+\r\n\/1Y1 |3       14| 2A2        | 1 | X | Z |\r\n 1A2 |4   74  13| \/2Y2       | 0 | 0 | 1 |\r\n\/1Y2 |5  368  12| 2A1        | 0 | 1 | 0 |\r\n 1A3 |6       11| \/2Y1       +---+---*---+\r\n\/1Y3 |7       10| 1A4\r\n GND |8        9| \/1Y4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74373\"><\/a><\/p>\n<h2>74373<\/h2>\n<p>8-bit 3-state transparent latch.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 20| VCC         |\/OE| LE| D | Q |\r\n Q1 |2       19| Q8          +===+===+===*===+\r\n D1 |3       18| D8          | 1 | X | X | Z |\r\n D2 |4       17| D7          | 0 | 0 | X | - |\r\n Q2 |5   74  16| Q7          | 0 | 1 | 0 | 0 |\r\n Q3 |6  373  15| Q6          | 0 | 1 | 1 | 1 |\r\n D3 |7       14| D6          +---+---+---*---+\r\n D4 |8       13| D5\r\n Q4 |9       12| Q5\r\nGND |10      11| LE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74374\"><\/a><\/p>\n<h2>74374<\/h2>\n<p>8-bit 3-state D flip-flop.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 20| VCC         |\/OE|CLK| D | Q |\r\n Q1 |2       19| Q8          +===+===+===*===+\r\n D1 |3       18| D8          | 1 | X | X | Z |\r\n D2 |4       17| D7          | 0 | \/ | 0 | 0 |\r\n Q2 |5   74  16| Q7          | 0 | \/ | 1 | 1 |\r\n Q3 |6  374  15| Q6          | 0 |!\/ | X | - |\r\n D3 |7       14| D6          +---+---+---*---+\r\n D4 |8       13| D5\r\n Q4 |9       12| Q5\r\nGND |10      11| CLK\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74375\"><\/a><\/p>\n<h2>74375<\/h2>\n<p>Dual 2-bit transparent latches with complementary outputs.<\/p>\n<pre>     +---+--+---+\r\n 1D1 |1  +--+ 16| VCC\r\n\/1Q1 |2       15| 2D1\r\n 1Q1 |3       14| \/2Q1\r\n 1LE |4   74  13| 2Q1\r\n 1Q2 |5  375  12| 2LE\r\n\/1Q2 |6       11| 2Q2\r\n 1D2 |7       10| \/2Q2\r\n GND |8        9| 2D2\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74376\"><\/a><\/p>\n<h2>74376<\/h2>\n<p>4-bit J-\/K flip-flop with reset.<\/p>\n<pre>     +---+--+---+            +---+---+---+----*---+---+\r\n\/RST |1  +--+ 16| VCC        | J |\/K |CLK|\/RST| Q |\/Q |\r\n  J1 |2       15| J4         +===+===+===+====*===+===+\r\n \/K1 |3       14| \/K4        | X | X | X |  0 | 0 | 1 |\r\n  Q1 |4   74  13| Q4         | 0 | 0 | \/ |  1 | 0 | 1 |\r\n  Q2 |5  376  12| Q3         | 0 | 1 | \/ |  1 | - | - |\r\n \/K2 |6       11| \/K3        | 1 | 0 | \/ |  1 |\/Q | Q |\r\n  J2 |7       10| J3         | 1 | 1 | \/ |  1 | 1 | 0 |\r\n GND |8        9| CLK        | X | X |!\/ |  1 | - | - |\r\n     +----------+            +---+---+---+----*---+---+\r\n<\/pre>\n<p><a name=\"74377\"><\/a><\/p>\n<h2>74377<\/h2>\n<p>8-bit D flip-flop with clock enable.<\/p>\n<pre>       +---+--+---+          +----+---+---*---+\r\n\/CLKEN |1  +--+ 20| VCC      |\/CEN|CLK| D | Q |\r\n    Q1 |2       19| Q8       +====+===+===*===+\r\n    D1 |3       18| D8       |  1 | X | X | - |\r\n    D2 |4       17| D7       |  0 | \/ | 0 | 0 |\r\n    Q2 |5   74  16| Q7       |  0 | \/ | 1 | 1 |\r\n    Q3 |6  377  15| Q6       |  0 |!\/ | X | - |\r\n    D3 |7       14| D6       +----+---+---*---+\r\n    D4 |8       13| D5\r\n    Q4 |9       12| Q5\r\n   GND |10      11| CLK\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74378\"><\/a><\/p>\n<h2>74378<\/h2>\n<p>6-bit D flip-flop with clock enable.<\/p>\n<pre>       +---+--+---+          +----+---+---*---+\r\n\/CLKEN |1  +--+ 16| VCC      |\/CEN|CLK| D | Q |\r\n    Q1 |2       15| Q6       +====+===+===*===+\r\n    D1 |3       14| D6       |  1 | X | X | - |\r\n    D2 |4   74  13| D5       |  0 | \/ | 0 | 0 |\r\n    Q2 |5  378  12| Q5       |  0 | \/ | 1 | 1 |\r\n    D3 |6       11| D4       |  0 |!\/ | X | - |\r\n    Q3 |7       10| Q4       +----+---+---*---+\r\n   GND |8        9| CLK\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74379\"><\/a><\/p>\n<h2>74379<\/h2>\n<p>6-bit D flip-flop with clock enable and complementary outputs.<\/p>\n<pre>       +---+--+---+          +----+---+---*---+---+\r\n\/CLKEN |1  +--+ 16| VCC      |\/CEN|CLK| D | Q |\/Q |\r\n    Q1 |2       15| Q4       +====+===+===*===+===+\r\n   \/Q1 |3       14| \/Q4      |  1 | X | X | - | - |\r\n    D1 |4   74  13| D4       |  0 | \/ | 0 | 0 | 1 |\r\n    D2 |5  379  12| D3       |  0 | \/ | 1 | 1 | 0 |\r\n   \/Q2 |6       11| \/Q3      |  0 |!\/ | X | - | - |\r\n    Q2 |7       10| Q3       +----+---+---*---+---+\r\n   GND |8        9| CLK\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74381\"><\/a><\/p>\n<h2>74381<\/h2>\n<p>4-bit 8-function arithmetic logic unit (ALU)<\/p>\n<pre>    +---+--+---+\r\n A1 |1  +--+ 20| VCC\r\n B1 |2       19| A2\r\n A0 |3       18| B2\r\n B0 |4       17| A3\r\n S0 |5   74  16| B3\r\n S1 |6  381  15| CIN\r\n S2 |7       14| \/P\r\n F0 |8       13| \/G\r\n F1 |9       12| F3\r\nGND |10      11| F2\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74382\"><\/a><\/p>\n<h2>74382<\/h2>\n<p>4-bit 8-function arithmetic logic unit (ALU) with ripple carry and overflow outputs.<\/p>\n<pre>    +---+--+---+\r\n A1 |1  +--+ 20| VCC\r\n B1 |2       19| A2\r\n A0 |3       18| B2\r\n B0 |4       17| A3\r\n S0 |5   74  16| B3\r\n S1 |6  382  15| CIN\r\n S2 |7       14| COUT\r\n F0 |8       13| OVR\r\n F1 |9       12| F3\r\nGND |10      11| F2\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74385\"><\/a><\/p>\n<h2>74385<\/h2>\n<p>Quad serial adder\/subtractor.<br \/>\nContains four independent adder\/subtractor elements with common clock and carry reset.<\/p>\n<pre>      +---+--+---+\r\n  CLK |1  +--+ 20| VCC\r\n   1S |2       19| 4S\r\n1S\/\/A |3       18| 4S\/\/A\r\n   1B |4       17| 4B\r\n   1A |5   74  16| 4A\r\n   2A |6  385  15| 3A\r\n   2B |7       14| 3B\r\n2S\/\/A |8       13| 3S\/\/A\r\n   2S |9       12| 3S\r\n  GND |10      11| RST\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74386\"><\/a><\/p>\n<h2>74386<\/h2>\n<p>Quad 2-input XOR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+                    _   _\r\n 1A |1  +--+ 14| VCC         | A | B | Y |       Y = A$B = (A.B)+(A.B)\r\n 1B |2       13| 4B          +===+===*===+\r\n 1Y |3  74   12| 4A          | 0 | 0 | 0 |\r\n 2Y |4  386  11| 4Y          | 0 | 1 | 1 |\r\n 2A |5       10| 3Y          | 1 | 0 | 1 |\r\n 2B |6        9| 3B          | 1 | 1 | 0 |\r\nGND |7        8| 3A          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74390\"><\/a><\/p>\n<h2>74390<\/h2>\n<p>Dual 4-bit asynchronous decade counters with separate \/2 and \/5 sections and reset.<\/p>\n<pre>       +---+--+---+\r\n\/1CLK0 |1  +--+ 16| VCC\r\n  1RST |2       15| \/2CLK0\r\n   1Q0 |3       14| 2RST\r\n\/1CLK1 |4   74  13| 2Q0\r\n   1Q1 |5  390  12| \/2CLK1\r\n   1Q2 |6       11| 2Q1\r\n   1Q3 |7       10| 2Q2\r\n   GND |8        9| 2Q3\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74393\"><\/a><\/p>\n<h2>74393<\/h2>\n<p>Dual 4-bit asynchronous binary counters with reset.<\/p>\n<pre>      +---+--+---+\r\n\/1CLK |1  +--+ 14| VCC\r\n 1RST |2       13| \/2CLK\r\n  1Q0 |3   74  12| 2RST\r\n  1Q1 |4  393  11| 2Q0\r\n  1Q2 |5       10| 2Q1\r\n  1Q3 |6        9| 2Q2\r\n  GND |7        8| 2Q3\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74395\"><\/a><\/p>\n<h2>74395<\/h2>\n<p>4-bit 3-state universal shift register with load and asynchronous reset.<\/p>\n<pre>       +---+--+---+\r\n  \/RST |1  +--+ 16| VCC\r\n     D |2       15| Y0\r\n    P0 |3       14| Y1\r\n    P1 |4   74  13| Y2\r\n    P2 |5  395  12| Y3\r\n    P3 |6       11| Q3\r\nLD\/\/SH |7       10| CLK\r\n   GND |8        9| \/OE\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74398\"><\/a><\/p>\n<h2>74398<\/h2>\n<p>8-to-4 line data selector\/multiplexer with output registers and complementary outputs.<\/p>\n<pre>    +---+--+---+\r\n  S |1  +--+ 20| VCC\r\n 1Y |2       19| 4Y\r\n\/1Y |3       18| \/4Y\r\n1A0 |4       17| 4A0\r\n1A1 |5   74  16| 4A1\r\n2A1 |6  398  15| 3A1\r\n2A0 |7       14| 3A0\r\n\/2Y |8       13| \/3Y\r\n 2Y |9       12| 3Y\r\nGND |10      11| CLK\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74399\"><\/a><\/p>\n<h2>74399<\/h2>\n<p>8-to-4 line inverting data selector\/multiplexer with output registers.<\/p>\n<pre>    +---+--+---+\r\n  S |1  +--+ 16| VCC\r\n 1Y |2       15| 4Y\r\n1A0 |3       14| 4A0\r\n1A1 |4   74  13| 4A1\r\n2A1 |5  399  12| 3A1\r\n2A0 |6       11| 3A0\r\n 2Y |7       10| 3Y\r\nGND |8        9| CLK\r\n    +----------+<\/pre>\n<p>&nbsp;<\/p>\n<h2>74423<\/h2>\n<p>Dual retriggerable monostable multivibrator with overriding reset.<br \/>\nCannot be triggered via reset input.<\/p>\n<pre>       +---+--+---+\r\n  \/1TR |1  +--+ 16| VCC\r\n   1TR |2       15| 1RCext\r\n \/1RST |3       14| 1Cext\r\n   \/1Q |4   74  13| 1Q\r\n    2Q |5  423  12| \/2Q\r\n 2Cext |6       11| \/2RST\r\n2RCext |7       10| 2TR\r\n   GND |8        9| \/2TR\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74465\"><\/a><\/p>\n<h2>74465<\/h2>\n<p>8-bit 3-state noninverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+\r\n\/OE1 |1  +--+ 20| VCC\r\n  A1 |2       19| \/OE2\r\n  Y1 |3       18| A8\r\n  A2 |4       17| Y8\r\n  Y2 |5  74   16| A7\r\n  A3 |6  465  15| Y7\r\n  Y3 |7       14| A6\r\n  A4 |8       13| Y6\r\n  Y4 |9       12| A5\r\n GND |10      11| Y5\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74490\"><\/a><\/p>\n<h2>74490<\/h2>\n<p>Dual 4-bit asynchronous decade counters with set(9) and reset.<\/p>\n<pre>      +---+--+---+\r\n\/1CLK |1  +--+ 16| VCC\r\n 1RST |2       15| \/2CLK\r\n  1QA |3       14| 2RST\r\n 1SET |4   74  13| 2Q0\r\n  1QB |5  490  12| 2SET\r\n  1QC |6       11| 2Q1\r\n  1QD |7       10| 2Q2\r\n  GND |8        9| 2Q3\r\n      +----------+\r\n<\/pre>\n<h2>74519<\/h2>\n<p>8-bit open-collector noninverting identity comparator with enable.<\/p>\n<pre>    +---+--+---+\r\n\/OE |1  +--+ 20| VCC\r\n A0 |2       19| A=B\r\n B0 |3       18| B7\r\n A1 |4       17| A7\r\n B1 |5   74  16| B6\r\n A2 |6  519  15| A6\r\n B2 |7       14| B5\r\n A3 |8       13| A5\r\n B3 |9       12| B4\r\nGND |10      11| A4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74520\"><\/a><\/p>\n<h2>74520<\/h2>\n<p>8-bit inverting identity comparator with itegrated 20k pull-up resistors and enable.<\/p>\n<pre>    +---+--+---+\r\n\/EN |1  +--+ 20| VCC\r\n A0 |2       19| A=B\r\n B0 |3       18| B7\r\n A1 |4       17| A7\r\n B1 |5   74  16| B6\r\n A2 |6  520  15| A6\r\n B2 |7       14| B5\r\n A3 |8       13| A5\r\n B3 |9       12| B4\r\nGND |10      11| A4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74521\"><\/a><\/p>\n<h2>74521<\/h2>\n<p>8-bit inverting identity comparator with enable.<\/p>\n<pre>    +---+--+---+\r\n\/OE |1  +--+ 20| VCC\r\n A0 |2       19| A=B\r\n B0 |3       18| B7\r\n A1 |4       17| A7\r\n B1 |5   74  16| B6\r\n A2 |6  521  15| A6\r\n B2 |7       14| B5\r\n A3 |8       13| A5\r\n B3 |9       12| B4\r\nGND |10      11| A4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74533\"><\/a><\/p>\n<h2>74533<\/h2>\n<p>8-bit 3-state inverting transparent latch.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 20| VCC         |\/OE| LE| D | Q |\r\n\/Q1 |2       19| \/Q8         +===+===+===*===+\r\n D1 |3       18| D8          | 1 | X | X | Z |\r\n D2 |4       17| D7          | 0 | 0 | X | - |\r\n\/Q2 |5   74  16| \/Q7         | 0 | 1 | 0 | 0 |\r\n\/Q3 |6  533  15| \/Q6         | 0 | 1 | 1 | 1 |\r\n D3 |7       14| D6          +---+---+---*---+\r\n D4 |8       13| D5\r\n\/Q4 |9       12| \/Q5\r\nGND |10      11| LE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74534\"><\/a><\/p>\n<h2>74534<\/h2>\n<p>8-bit 3-state inverting D flip-flop.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 20| VCC         |\/OE|CLK| D |\/Q |\r\n\/Q1 |2       19| \/Q8         +===+===+===*===+\r\n D1 |3       18| D8          | 1 | X | X | Z |\r\n D2 |4       17| D7          | 0 | \/ | 0 | 1 |\r\n\/Q2 |5   74  16| \/Q7         | 0 | \/ | 1 | 0 |\r\n\/Q3 |6  534  15| \/Q6         | 0 |!\/ | X | - |\r\n D3 |7       14| D6          +---+---+---*---+\r\n D4 |8       13| D5\r\n\/Q4 |9       12| \/Q5\r\nGND |10      11| CLK\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74540\"><\/a><\/p>\n<h2>74540<\/h2>\n<p>8-bit 3-state inverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+\r\n\/OE1 |1  +--+ 20| VCC\r\n  A1 |2       19| \/OE2\r\n  A2 |3       18| \/Y1\r\n  A3 |4       17| \/Y2\r\n  A4 |5   74  16| \/Y3\r\n  A5 |6  540  15| \/Y4\r\n  A6 |7       14| \/Y5\r\n  A7 |8       13| \/Y6\r\n  A8 |9       12| \/Y7\r\n GND |10      11| \/Y8\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74541\"><\/a><\/p>\n<h2>74541<\/h2>\n<p>8-bit 3-state noninverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+\r\n\/OE1 |1  +--+ 20| VCC\r\n  A1 |2       19| \/OE2\r\n  A2 |3       18| Y1\r\n  A3 |4       17| Y2\r\n  A4 |5   74  16| Y3\r\n  A5 |6  541  15| Y4\r\n  A6 |7       14| Y5\r\n  A7 |8       13| Y6\r\n  A8 |9       12| Y7\r\n GND |10      11| Y8\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74543\"><\/a><\/p>\n<h2>74543<\/h2>\n<p>8-bit 3-state noninverting registered transceiver.<\/p>\n<pre>      +---+--+---+\r\n\/LEBA |1  +--+ 24| VCC\r\n \/GBA |2       23| \/CEBA\r\n   A1 |3       22| B1\r\n   A2 |4       21| B2\r\n   A3 |5       20| B3\r\n   A4 |6   74  19| B4\r\n   A5 |7  543  18| B5\r\n   A6 |8       17| B6\r\n   A7 |9       16| B7\r\n   A8 |10      15| B8\r\n\/CEAB |11      14| \/LEAB\r\n  GND |12      13| \/GAB\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74544\"><\/a><\/p>\n<h2>74544<\/h2>\n<p>8-bit 3-state inverting registered transceiver.<\/p>\n<pre>      +---+--+---+\r\n\/LEBA |1  +--+ 24| VCC\r\n \/GBA |2       23| \/CEBA\r\n   A1 |3       22| B1\r\n   A2 |4       21| B2\r\n   A3 |5       20| B3\r\n   A4 |6   74  19| B4\r\n   A5 |7  544  18| B5\r\n   A6 |8       17| B6\r\n   A7 |9       16| B7\r\n   A8 |10      15| B8\r\n\/CEAB |11      14| \/LEAB\r\n  GND |12      13| \/GAB\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74561\"><\/a><\/p>\n<h2>74561<\/h2>\n<p>4-bit 3-state synchronous binary counter with sync\/async load, sync\/async reset, and ripple\/clocked carry output.<\/p>\n<pre>      +---+--+---+\r\n \/ALD |1  +--+ 20| VCC\r\n  CLK |2       19| RCO\r\n   P0 |3       18| CCO\r\n   P1 |4       17| \/OE\r\n   P2 |5   74  16| Q0\r\n   P3 |6  561  15| Q1\r\n  ENP |7       14| Q2\r\n\/ARST |8       13| Q3\r\n\/SRST |9       12| ENT\r\n  GND |10      11| \/SLD\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74563\"><\/a><\/p>\n<h2>74563<\/h2>\n<p>8-bit 3-state inverting transparent latch.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 20| VCC         |\/OE| LE| D |\/Q |\r\n D1 |2       19| \/Q1         +===+===+===*===+\r\n D2 |3       18| \/Q2         | 1 | X | X | Z |\r\n D3 |4       17| \/Q3         | 0 | 0 | X | - |\r\n D4 |5   74  16| \/Q4         | 0 | 1 | 0 | 1 |\r\n D5 |6  563  15| \/Q5         | 0 | 1 | 1 | 0 |\r\n D6 |7       14| \/Q6         +---+---+---*---+\r\n D7 |8       13| \/Q7\r\n D8 |9       12| \/Q8\r\nGND |10      11| LE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74564\"><\/a><\/p>\n<h2>74564<\/h2>\n<p>8-bit 3-state inverting D flip-flop.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 20| VCC         |\/OE|CLK| D |\/Q |\r\n D1 |2       19| \/Q1         +===+===+===*===+\r\n D2 |3       18| \/Q2         | 1 | X | X | Z |\r\n D3 |4       17| \/Q3         | 0 | \/ | 0 | 1 |\r\n D4 |5   74  16| \/Q4         | 0 | \/ | 1 | 0 |\r\n D5 |6  564  15| \/Q5         | 0 |!\/ | X | - |\r\n D6 |7       14| \/Q6         +---+---+---*---+\r\n D7 |8       13| \/Q7\r\n D8 |9       12| \/Q8\r\nGND |10      11| CLK\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74568\"><\/a><\/p>\n<h2>74568<\/h2>\n<p>4-bit 3-state synchronous decade up\/down counter with load, sync\/async reset, and ripple\/clocked carry output.<\/p>\n<pre>      +---+--+---+\r\n U\/\/D |1  +--+ 20| VCC\r\n  CLK |2       19| \/RCO\r\n   P0 |3       18| \/CCO\r\n   P1 |4       17| \/OE\r\n   P2 |5   74  16| Q0\r\n   P3 |6  568  15| Q1\r\n \/ENP |7       14| Q2\r\n\/ARST |8       13| Q3\r\n\/SRST |9       12| \/ENT\r\n  GND |10      11| \/LOAD\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74569\"><\/a><\/p>\n<h2>74569<\/h2>\n<p>4-bit 3-state synchronous binary up\/down counter with load, sync\/async reset, and ripple\/clocked carry output.<\/p>\n<pre>      +---+--+---+\r\n U\/\/D |1  +--+ 20| VCC\r\n  CLK |2       19| \/RCO\r\n   P0 |3       18| \/CCO\r\n   P1 |4       17| \/OE\r\n   P2 |5   74  16| Q0\r\n   P3 |6  569  15| Q1\r\n \/ENP |7       14| Q2\r\n\/ARST |8       13| Q3\r\n\/SRST |9       12| \/ENT\r\n  GND |10      11| \/LOAD\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74573\"><\/a><\/p>\n<h2>74573<\/h2>\n<p>8-bit 3-state transparent latch.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 20| VCC         |\/OE| LE| D |\/Q |\r\n D1 |2       19| Q1          +===+===+===*===+\r\n D2 |3       18| Q2          | 1 | X | X | Z |\r\n D3 |4       17| Q3          | 0 | 0 | X | - |\r\n D4 |5   74  16| Q4          | 0 | 1 | 0 | 0 |\r\n D5 |6  573  15| Q5          | 0 | 1 | 1 | 1 |\r\n D6 |7       14| Q6          +---+---+---*---+\r\n D7 |8       13| Q7\r\n D8 |9       12| Q8\r\nGND |10      11| LE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74574\"><\/a><\/p>\n<h2>74574<\/h2>\n<p>8-bit 3-state D flip-flop.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 20| VCC         |\/OE|CLK| D | Q |\r\n D1 |2       19| Q1          +===+===+===*===+\r\n D2 |3       18| Q2          | 1 | X | X | Z |\r\n D3 |4       17| Q3          | 0 | \/ | 0 | 0 |\r\n D4 |5   74  16| Q4          | 0 | \/ | 1 | 1 |\r\n D5 |6  574  15| Q5          | 0 |!\/ | X | - |\r\n D6 |7       14| Q6          +---+---+---*---+\r\n D7 |8       13| Q7\r\n D8 |9       12| Q8\r\nGND |10      11| CLK\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74575\"><\/a><\/p>\n<h2>74575<\/h2>\n<p>8-bit 3-state D flip-flop with reset.<\/p>\n<pre>     +---+--+---+            +----+---+---+---*---+\r\n\/RST |1  +--+ 24| VCC        |\/RST|\/OE|CLK| D | Q |\r\n \/OE |2       23|            +====+===+===+===*===+\r\n  D1 |3       22| Q1         |  0 | 1 | X | X | Z |\r\n  D2 |4       21| Q2         |  X | 0 | X | X | 0 |\r\n  D3 |5       20| Q3         |  1 | 0 | \/ | 0 | 0 |\r\n  D4 |6   74  19| Q4         |  1 | 0 | \/ | 1 | 1 |\r\n  D5 |7  575  18| Q5         |  1 | 0 |!\/ | X | - |\r\n  D6 |8       17| Q6         +----+---+---+---*---+\r\n  D7 |9       16| Q7\r\n  D8 |10      15| Q8\r\n     |11      14| CLK\r\n GND |12      13|\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74576\"><\/a><\/p>\n<h2>74576<\/h2>\n<p>8-bit 3-state inverting D flip-flop.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 20| VCC         |\/OE|CLK| D |\/Q |\r\n D1 |2       19| \/Q1         +===+===+===*===+\r\n D2 |3       18| \/Q2         | 1 | X | X | Z |\r\n D3 |4       17| \/Q3         | 0 | \/ | 0 | 1 |\r\n D4 |5   74  16| \/Q4         | 0 | \/ | 1 | 0 |\r\n D5 |6  576  15| \/Q5         | 0 |!\/ | X | - |\r\n D6 |7       14| \/Q6         +---+---+---*---+\r\n D7 |8       13| \/Q7\r\n D8 |9       12| \/Q8\r\nGND |10      11| CLK\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74577\"><\/a><\/p>\n<h2>74577<\/h2>\n<p>8-bit 3-state inverting D flip-flop with reset.<\/p>\n<pre>     +---+--+---+            +----+---+---+---*---+\r\n\/RST |1  +--+ 24| VCC        |\/RST|\/OE|CLK| D |\/Q |\r\n \/OE |2       23|            +====+===+===+===*===+\r\n  D1 |3       22| \/Q1        |  0 | 1 | X | X | Z |\r\n  D2 |4       21| \/Q2        |  X | 0 | X | X | 1 |\r\n  D3 |5       20| \/Q3        |  1 | 0 | \/ | 0 | 1 |\r\n  D4 |6   74  19| \/Q4        |  1 | 0 | \/ | 1 | 0 |\r\n  D5 |7  577  18| \/Q5        |  1 | 0 |!\/ | X | - |\r\n  D6 |8       17| \/Q6        +----+---+---+---*---+\r\n  D7 |9       16| \/Q7\r\n  D8 |10      15| \/Q8\r\n     |11      14| CLK\r\n GND |12      13|\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74580\"><\/a><\/p>\n<h2>74580<\/h2>\n<p>8-bit 3-state inverting transparent latch.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 20| VCC         |\/OE| LE| D |\/Q |\r\n D1 |2       19| \/Q1         +===+===+===*===+\r\n D2 |3       18| \/Q2         | 1 | X | X | Z |\r\n D3 |4       17| \/Q3         | 0 | 0 | X | - |\r\n D4 |5   74  16| \/Q4         | 0 | 1 | 0 | 1 |\r\n D5 |6  580  15| \/Q5         | 0 | 1 | 1 | 0 |\r\n D6 |7       14| \/Q6         +---+---+---*---+\r\n D7 |8       13| \/Q7\r\n D8 |9       12| \/Q8\r\nGND |10      11| LE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74589\"><\/a><\/p>\n<h2>74589<\/h2>\n<p>8-bit 3-state parallel-in serial-out shift register with input registers.<br \/>\nIndependent clocks for shift and storage registers.<\/p>\n<pre>    +---+--+---+\r\n P1 |1  +--+ 16| VCC\r\n P2 |2       15| P0\r\n P3 |3       14| D\r\n P4 |4   74  13| SH\/\/LD\r\n P5 |5  589  12| RCLK\r\n P6 |6       11| SCLK\r\n P7 |7       10| \/OE\r\nGND |8        9| Q7\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74590\"><\/a><\/p>\n<h2>74590<\/h2>\n<p>8-bit 3-state synchronous binary counter with reset and output registers.<br \/>\nSeparate clocks for both counter and storage register, ripple carry output.<\/p>\n<pre>    +---+--+---+\r\n Q1 |1  +--+ 16| VCC\r\n Q2 |2       15| Q0\r\n Q3 |3       14| \/OE\r\n Q4 |4   74  13| RCLK\r\n Q5 |5  590  12| \/CLKEN\r\n Q6 |6       11| CCLK\r\n Q7 |7       10| \/CRST\r\nGND |8        9| \/RCO\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74592\"><\/a><\/p>\n<h2>74592<\/h2>\n<p>8-bit synchronous binary counter with input registers.<br \/>\nSeparate clocks for counter and input register. Counter outputs only internally connected but ripple carry and clock outputs available.<\/p>\n<pre>    +---+--+---+\r\n P1 |1  +--+ 16| VCC\r\n P2 |2       15| P0\r\n P3 |3       14| \/CLOAD\r\n P4 |4   74  13| RCLK\r\n P5 |5  592  12| \/CLKEN\r\n P6 |6       11| CCLK\r\n P7 |7       10| \/CRST\r\nGND |8        9| \/RCO\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74593\"><\/a><\/p>\n<h2>74593<\/h2>\n<p>8-bit 3-state synchronous binary counter with input registers and ripple carry and clock outputs. Separate clocks for counter and input registers.<\/p>\n<pre>     +---+--+---+\r\n  P0 |1  +--+ 20| VCC\r\n  P1 |2       19| OE\r\n  P2 |3       18| \/OE\r\n  P3 |4       17| \/RCLKEN\r\n  P4 |5   74  16| RCLK\r\n  P5 |6  593  15| CLKEN\r\n  P6 |7       14| \/CLKEN\r\n  P7 |8       13| CCLK\r\n\/CLD |9       12| \/CRST\r\n GND |10      11| \/RCO\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74594\"><\/a><\/p>\n<h2>74594<\/h2>\n<p>8-bit serial-in parallel-out shift register with output registers and two asynchronous resets. Independent clocks and resets for shift and storage registers.<\/p>\n<pre>    +---+--+---+\r\n Y1 |1  +--+ 16| VCC\r\n Y2 |2       15| Y0\r\n Y3 |3       14| A\r\n Y4 |4   74  13| \/RRST\r\n Y5 |5  594  12| RCLK\r\n Y6 |6       11| SCLK\r\n Y7 |7       10| \/SRST\r\nGND |8        9| Q7\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74595\"><\/a><\/p>\n<h2>74595<\/h2>\n<p>8-bit 3-state serial-in parallel-out shift register with output registers and asynchronous reset. Independent clocks for shift and storage registers.<\/p>\n<pre>    +---+--+---+\r\n Y1 |1  +--+ 16| VCC\r\n Y2 |2       15| Y0\r\n Y3 |3       14| A\r\n Y4 |4   74  13| \/OE\r\n Y5 |5  595  12| RCLK\r\n Y6 |6       11| SCLK\r\n Y7 |7       10| \/RST\r\nGND |8        9| Q7\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74596\"><\/a><\/p>\n<h2>74596<\/h2>\n<p>8-bit open-collector serial-in parallel-out shift register with output registers and asynchronous reset. Independent clocks for shift and storage registers.<\/p>\n<pre>    +---+--+---+\r\n Y1 |1  +--+ 16| VCC\r\n Y2 |2       15| Y0\r\n Y3 |3       14| D\r\n Y4 |4   74  13| \/OE\r\n Y5 |5  596  12| RCLK\r\n Y6 |6       11| SCLK\r\n Y7 |7       10| \/RST\r\nGND |8        9| Q7\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74597\"><\/a><\/p>\n<h2>74597<\/h2>\n<p>8-bit parallel-in serial-out shift register with input registers and asynchronous reset. Independent clocks for shift and storage registers.<\/p>\n<pre>    +---+--+---+\r\n P1 |1  +--+ 16| VCC\r\n P2 |2       15| P0\r\n P3 |3       14| D\r\n P4 |4   74  13| SH\/\/LD\r\n P5 |5  597  12| RCLK\r\n P6 |6       11| SCLK\r\n P7 |7       10| \/RST\r\nGND |8        9| Q7\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74598\"><\/a><\/p>\n<h2>74598<\/h2>\n<p>8-bit 3-state shift register with input registers, asynchronous reset and selectable serial input. Independent clocks for shift and storage registers.<\/p>\n<pre>       +---+--+---+\r\n    P0 |1  +--+ 20| VCC\r\n    P1 |2       19| S\r\n    P2 |3       18| D\r\n    P3 |4       17| E\r\n    P4 |5   74  16| \/OE\r\n    P5 |6  598  15| RCLK\r\n    P6 |7       14| \/SCE\r\n    P7 |8       13| SCLK\r\nSH\/\/LD |9       12| \/RST\r\n   GND |10      11| Q7\r\n       +----------+<\/pre>\n<h2>74620<\/h2>\n<p>8-bit 3-state inverting bus transceiver.<br \/>\nTwo enable pins control output enables, one active high and one active low.<\/p>\n<pre>    +---+--+---+\r\nGAB |1  +--+ 20| VCC\r\n A1 |2       19| \/GBA\r\n A2 |3       18| B1\r\n A3 |4       17| B2\r\n A4 |5  74   16| B3\r\n A5 |6  620  15| B4\r\n A6 |7       14| B5\r\n A7 |8       13| B6\r\n A8 |9       12| B7\r\nGND |10      11| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74621\"><\/a><\/p>\n<h2>74621<\/h2>\n<p>8-bit open-collector noninverting bus transceiver.<br \/>\nTwo enable pins control output enables, one active high and one active low.<\/p>\n<pre>    +---+--+---+\r\nGAB |1  +--+ 20| VCC\r\n A1 |2       19| \/GBA\r\n A2 |3       18| B1\r\n A3 |4       17| B2\r\n A4 |5  74   16| B3\r\n A5 |6  621  15| B4\r\n A6 |7       14| B5\r\n A7 |8       13| B6\r\n A8 |9       12| B7\r\nGND |10      11| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74623\"><\/a><\/p>\n<h2>74623<\/h2>\n<p>8-bit 3-state noninverting bus transceiver.<br \/>\nTwo enable pins control output enables, one active high and one active low.<\/p>\n<pre>    +---+--+---+\r\nGAB |1  +--+ 20| VCC\r\n A1 |2       19| \/GBA\r\n A2 |3       18| B1\r\n A3 |4       17| B2\r\n A4 |5  74   16| B3\r\n A5 |6  623  15| B4\r\n A6 |7       14| B5\r\n A7 |8       13| B6\r\n A8 |9       12| B7\r\nGND |10      11| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74638\"><\/a><\/p>\n<h2>74638<\/h2>\n<p>8-bit 3-state\/open-collector inverting bus transceiver.<br \/>\nEnable and direction pins control output enables.<\/p>\n<pre>    +---+--+---+\r\nDIR |1  +--+ 20| VCC\r\n A1 |2       19| \/OE\r\n A2 |3       18| B1\r\n A3 |4       17| B2\r\n A4 |5  74   16| B3\r\n A5 |6  638  15| B4\r\n A6 |7       14| B5\r\n A7 |8       13| B6\r\n A8 |9       12| B7\r\nGND |10      11| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74639\"><\/a><\/p>\n<h2>74639<\/h2>\n<p>8-bit 3-state\/open-collector noninverting bus transceiver.<br \/>\nEnable and direction pins control output enables.<\/p>\n<pre>    +---+--+---+\r\nDIR |1  +--+ 20| VCC\r\n A1 |2       19| \/OE\r\n A2 |3       18| B1\r\n A3 |4       17| B2\r\n A4 |5  74   16| B3\r\n A5 |6  639  15| B4\r\n A6 |7       14| B5\r\n A7 |8       13| B6\r\n A8 |9       12| B7\r\nGND |10      11| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74640\"><\/a><\/p>\n<h2>74640<\/h2>\n<p>8-bit 3-state inverting bus transceiver.<br \/>\nEnable and direction pins control output enables.<\/p>\n<pre>    +---+--+---+             +---+---*---+---+\r\nDIR |1  +--+ 20| VCC         |\/EN|DIR| A | B |\r\n A1 |2       19| \/EN         +===+===*===+===+\r\n A2 |3       18| B1          | 1 | X | Z | Z |\r\n A3 |4       17| B2          | 0 | 0 |\/B | Z |\r\n A4 |5  74   16| B3          | 0 | 1 | Z |\/A |\r\n A5 |6  640  15| B4          +---+---*---+---+\r\n A6 |7       14| B5\r\n A7 |8       13| B6\r\n A8 |9       12| B7\r\nGND |10      11| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74641\"><\/a><\/p>\n<h2>74641<\/h2>\n<p>8-bit 3-state noninverting bus transceiver.<br \/>\nEnable and direction pins control output enables.<\/p>\n<pre>    +---+--+---+\r\nDIR |1  +--+ 20| VCC\r\n A1 |2       19| \/OE\r\n A2 |3       18| B1\r\n A3 |4       17| B2\r\n A4 |5  74   16| B3\r\n A5 |6  641  15| B4\r\n A6 |7       14| B5\r\n A7 |8       13| B6\r\n A8 |9       12| B7\r\nGND |10      11| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74642\"><\/a><\/p>\n<h2>74642<\/h2>\n<p>8-bit open-collector inverting bus transceiver.<br \/>\nEnable and direction pins control output enables.<\/p>\n<pre>    +---+--+---+\r\nDIR |1  +--+ 20| VCC\r\n A1 |2       19| \/OE\r\n A2 |3       18| B1\r\n A3 |4       17| B2\r\n A4 |5  74   16| B3\r\n A5 |6  642  15| B4\r\n A6 |7       14| B5\r\n A7 |8       13| B6\r\n A8 |9       12| B7\r\nGND |10      11| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74643\"><\/a><\/p>\n<h2>74643<\/h2>\n<p>8-bit 3-state inverting\/noninverting bus transceiver.<br \/>\nEnable and direction pins control output enables.<\/p>\n<pre>    +---+--+---+             +---+---*---+---+\r\nDIR |1  +--+ 20| VCC         |\/EN|DIR| A | B |\r\n A1 |2       19| \/EN         +===+===*===+===+\r\n A2 |3       18| B1          | 1 | X | Z | Z |\r\n A3 |4       17| B2          | 0 | 0 | B | Z |\r\n A4 |5  74   16| B3          | 0 | 1 | Z |\/A |\r\n A5 |6  643  15| B4          +---+---*---+---+\r\n A6 |7       14| B5\r\n A7 |8       13| B6\r\n A8 |9       12| B7\r\nGND |10      11| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74645\"><\/a><\/p>\n<h2>74645<\/h2>\n<p>8-bit 3-state noninverting bus transceiver.<br \/>\nEnable and direction pins control output enables.<\/p>\n<pre>    +---+--+---+\r\nDIR |1  +--+ 20| VCC\r\n A1 |2       19| \/OE\r\n A2 |3       18| B1\r\n A3 |4       17| B2\r\n A4 |5  74   16| B3\r\n A5 |6  645  15| B4\r\n A6 |7       14| B5\r\n A7 |8       13| B6\r\n A8 |9       12| B7\r\nGND |10      11| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74646\"><\/a><\/p>\n<h2>74646<\/h2>\n<p>8-bit 3-state noninverting registered transceiver.<\/p>\n<pre>    +---+--+---+\r\nCAB |1  +--+ 24| VCC\r\nSAB |2       23| CBA\r\nDIR |3       22| SBA\r\n A1 |4       21| \/OE\r\n A2 |5       20| B1\r\n A3 |6   74  19| B2\r\n A4 |7  646  18| B3\r\n A5 |8       17| B4\r\n A6 |9       16| B5\r\n A7 |10      15| B6\r\n A8 |11      14| B7\r\nGND |12      13| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74648\"><\/a><\/p>\n<h2>74648<\/h2>\n<p>8-bit 3-state inverting registered transceiver.<\/p>\n<pre>    +---+--+---+\r\nCAB |1  +--+ 24| VCC\r\nSAB |2       23| CBA\r\nDIR |3       22| SBA\r\n A1 |4       21| \/OE\r\n A2 |5       20| B1\r\n A3 |6   74  19| B2\r\n A4 |7  648  18| B3\r\n A5 |8       17| B4\r\n A6 |9       16| B5\r\n A7 |10      15| B6\r\n A8 |11      14| B7\r\nGND |12      13| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74651\"><\/a><\/p>\n<h2>74651<\/h2>\n<p>8-bit 3-state inverting registered transceiver.<\/p>\n<pre>    +---+--+---+\r\nCAB |1  +--+ 24| VCC\r\nSAB |2       23| CBA\r\nGAB |3       22| SBA\r\n A1 |4       21| \/GBA\r\n A2 |5       20| B1\r\n A3 |6   74  19| B2\r\n A4 |7  651  18| B3\r\n A5 |8       17| B4\r\n A6 |9       16| B5\r\n A7 |10      15| B6\r\n A8 |11      14| B7\r\nGND |12      13| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74652\"><\/a><\/p>\n<h2>74652<\/h2>\n<p>8-bit 3-state noninverting registered transceiver.<\/p>\n<pre>    +---+--+---+\r\nCAB |1  +--+ 24| VCC\r\nSAB |2       23| CBA\r\nGAB |3       22| SBA\r\n A1 |4       21| \/GBA\r\n A2 |5       20| B1\r\n A3 |6   74  19| B2\r\n A4 |7  652  18| B3\r\n A5 |8       17| B4\r\n A6 |9       16| B5\r\n A7 |10      15| B6\r\n A8 |11      14| B7\r\nGND |12      13| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74653\"><\/a><\/p>\n<h2>74653<\/h2>\n<p>8-bit 3-state\/open-collector inverting registered transceiver.<\/p>\n<pre>    +---+--+---+\r\nCAB |1  +--+ 24| VCC\r\nSAB |2       23| CBA\r\nGAB |3       22| SBA\r\n A1 |4       21| \/GBA\r\n A2 |5       20| B1\r\n A3 |6   74  19| B2\r\n A4 |7  653  18| B3\r\n A5 |8       17| B4\r\n A6 |9       16| B5\r\n A7 |10      15| B6\r\n A8 |11      14| B7\r\nGND |12      13| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74654\"><\/a><\/p>\n<h2>74654<\/h2>\n<p>8-bit 3-state\/open-collector noninverting registered transceiver.<\/p>\n<pre>    +---+--+---+\r\nCAB |1  +--+ 24| VCC\r\nSAB |2       23| CBA\r\nGAB |3       22| SBA\r\n A1 |4       21| \/GBA\r\n A2 |5       20| B1\r\n A3 |6   74  19| B2\r\n A4 |7  654  18| B3\r\n A5 |8       17| B4\r\n A6 |9       16| B5\r\n A7 |10      15| B6\r\n A8 |11      14| B7\r\nGND |12      13| B8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74657\"><\/a><\/p>\n<h2>74657<\/h2>\n<p>8-bit 3-state noninverting bus transceiver with parity generator\/checker.<br \/>\nEnable and direction pins control output enables.<\/p>\n<pre>       +---+--+---+\r\n   DIR |1  +--+ 24| \/OE\r\n    A1 |2       23| B1\r\n    A2 |3       22| B2\r\n    A3 |4       21| B3\r\n    A4 |5       20| B4\r\n    A5 |6   74  19| GND\r\n   VCC |7  657  18| GND\r\n    A6 |8       17| B5\r\n    A7 |9       16| B6\r\n    A8 |10      15| B7\r\n  O\/\/E |11      14| B8\r\n\/ERROR |12      13| PAR\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74666\"><\/a><\/p>\n<h2>74666<\/h2>\n<p>8-bit 3-state transparent latch with readback, set and reset.<\/p>\n<pre>      +---+--+---+\r\n\/OERB |1  +--+ 24| VCC\r\n \/OE1 |2       23| \/OE2\r\n   D1 |3       22| Q1\r\n   D2 |4       21| Q2\r\n   D3 |5       20| Q3\r\n   D4 |6   74  19| Q4\r\n   D5 |7  666  18| Q5\r\n   D6 |8       17| Q6\r\n   D7 |9       16| Q7\r\n   D8 |10      15| Q8\r\n \/RST |11      14| \/SET\r\n  GND |12      13| LE\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74669\"><\/a><\/p>\n<h2>74669<\/h2>\n<p>4-bit synchronous binary up\/down counter with load and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\nU\/\/D |1  +--+ 16| VCC\r\n CLK |2       15| \/RCO\r\n  P0 |3       14| Q0\r\n  P1 |4   74  13| Q1\r\n  P2 |5  169  12| Q2\r\n  P3 |6       11| Q3\r\n\/ENP |7       10| \/ENT\r\n GND |8        9| \/LOAD\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74670\"><\/a><\/p>\n<h2>74670<\/h2>\n<p>4&#215;4-bit 3-state dual-port register file.<\/p>\n<pre>    +---+--+---+\r\n D2 |1  +--+ 16| VCC\r\n D3 |2       15| D1\r\n D4 |3       14| WA0\r\nRA1 |4   74  13| WA1\r\nRA0 |5  670  12| \/WR\r\n Q4 |6       11| \/RD\r\n Q3 |7       10| Q1\r\nGND |8        9| Q2\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74673\"><\/a><\/p>\n<h2>74673<\/h2>\n<p>16-bit 3-state universal shift register with storage register, reset and 16-bit rotate function.<\/p>\n<pre>         +---+--+---+\r\n     \/CE |1  +--+ 24| VCC\r\n    \/CLK |2       23| P15\r\n R\/\/W S0 |3       22| P14\r\n\/RRST S1 |4       21| P13\r\n L\/\/S S2 |5       20| P12\r\n  D0\/Q15 |6   74  19| P11\r\n      P0 |7  673  18| P10\r\n      P1 |8       17| P9\r\n      P2 |9       16| P8\r\n      P3 |10      15| P7\r\n      P4 |11      14| P6\r\n     GND |12      13| P5\r\n         +----------+\r\n<\/pre>\n<p><a name=\"74674\"><\/a><\/p>\n<h2>74674<\/h2>\n<p>16-bit 3-state universal shift register with 16-bit rotate function.<\/p>\n<pre>        +---+--+---+         +---+---+---*----------------------------+\r\n    \/CE |1  +--+ 24| VCC     |\/CE| S1| S0| Function                   |\r\n   \/CLK |2       23| P15     +===+===+===*============================+\r\nR\/\/W S0 |3       22| P14     | 1 | X | X | hold, P0..15=Z             |\r\n        |4       21| P13     | 0 | X | 0 | serial-in parallel out     |\r\nL\/\/S S1 |5       20| P12     | 0 | 0 | 1 | serial&amp;parallel out rotate |\r\n D0\/Q15 |6   74  19| P11     | 0 | 1 | 1 | parallel load              |\r\n     P0 |7  674  18| P10     +---+---+---*----------------------------+\r\n     P1 |8       17| P9\r\n     P2 |9       16| P8\r\n     P3 |10      15| P7\r\n     P4 |11      14| P6\r\n    GND |12      13| P5\r\n        +----------+\r\n<\/pre>\n<p><a name=\"74677\"><\/a><\/p>\n<h2>74677<\/h2>\n<p>16-bit inverting address comparator with enable.<\/p>\n<pre>    +---+--+---+\r\n A1 |1  +--+ 24| VCC\r\n A2 |2       23| \/EN\r\n A3 |3       22| Y\r\n A4 |4       21| P3\r\n A5 |5       20| P2\r\n A6 |6   74  19| P1\r\n A7 |7  677  18| P0\r\n A8 |8       17| A16\r\n A9 |9       16| A15\r\nA10 |10      15| A14\r\nA11 |11      14| A13\r\nGND |12      13| A12\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74682\"><\/a><\/p>\n<h2>74682<\/h2>\n<p>8-bit inverting magnitude comparator with integrated 100k pull-up resistors.<\/p>\n<pre>     +---+--+---+\r\n\/A&gt;B |1  +--+ 20| VCC\r\n  A0 |2       19| A=B\r\n  B0 |3       18| B7\r\n  A1 |4       17| A7\r\n  B1 |5   74  16| B6\r\n  A2 |6  682  15| A6\r\n  B2 |7       14| B5\r\n  A3 |8       13| A5\r\n  B3 |9       12| B4\r\n GND |10      11| A4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74684\"><\/a><\/p>\n<h2>74684<\/h2>\n<p>8-bit inverting magnitude comparator.<\/p>\n<pre>     +---+--+---+\r\n\/A&gt;B |1  +--+ 20| VCC\r\n  A0 |2       19| A=B\r\n  B0 |3       18| B7\r\n  A1 |4       17| A7\r\n  B1 |5   74  16| B6\r\n  A2 |6  684  15| A6\r\n  B2 |7       14| B5\r\n  A3 |8       13| A5\r\n  B3 |9       12| B4\r\n GND |10      11| A4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74686\"><\/a><\/p>\n<h2>74686<\/h2>\n<p>8-bit inverting magnitude comparator with enable.<\/p>\n<pre>     +---+--+---+\r\n\/A&gt;B |1  +--+ 24| VCC\r\n\/EN1 |2       23| \/EN2\r\n  A0 |3       22| \/A=B\r\n  B0 |4       21| B7\r\n  A1 |5       20| A7\r\n  B1 |6   74  19|\r\n     |7  686  18| B6\r\n  A2 |8       17| A6\r\n  B2 |9       16| B5\r\n  A3 |10      15| A5\r\n  B3 |11      14| B4\r\n GND |12      13| A4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74687\"><\/a><\/p>\n<h2>74687<\/h2>\n<p>8-bit open-collector inverting magnitude comparator with enable.<\/p>\n<pre>     +---+--+---+\r\n\/A&gt;B |1  +--+ 24| VCC\r\n\/EN1 |2       23| \/EN2\r\n  A0 |3       22| \/A=B\r\n  B0 |4       21| B7\r\n  A1 |5       20| A7\r\n  B1 |6   74  19|\r\n     |7  687  18| B6\r\n  A2 |8       17| A6\r\n  B2 |9       16| B5\r\n  A3 |10      15| A5\r\n  B3 |11      14| B4\r\n GND |12      13| A4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74688\"><\/a><\/p>\n<h2>74688<\/h2>\n<p>8-bit inverting identity comparator with enable.<\/p>\n<pre>    +---+--+---+\r\n\/EN |1  +--+ 20| VCC\r\n A0 |2       19| \/A=B\r\n B0 |3       18| B7\r\n A1 |4       17| A7\r\n B1 |5   74  16| B6\r\n A2 |6  688  15| A6\r\n B2 |7       14| B5\r\n A3 |8       13| A5\r\n B3 |9       12| B4\r\nGND |10      11| A4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74689\"><\/a><\/p>\n<h2>74689<\/h2>\n<p>8-bit open-collector inverting identity comparator with enable.<\/p>\n<pre>    +---+--+---+\r\n\/EN |1  +--+ 20| VCC\r\n A0 |2       19| \/A=B\r\n B0 |3       18| B7\r\n A1 |4       17| A7\r\n B1 |5   74  16| B6\r\n A2 |6  689  15| A6\r\n B2 |7       14| B5\r\n A3 |8       13| A5\r\n B3 |9       12| B4\r\nGND |10      11| A4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74691\"><\/a><\/p>\n<h2>74691<\/h2>\n<p>4-bit 3-state synchronous binary counter with output registers, asynchronous reset and ripple carry output. Multiplexed register\/counter outputs.<\/p>\n<pre>      +---+--+---+\r\n\/CRST |1  +--+ 20| VCC\r\n CCLK |2       19| RCO\r\n   P0 |3       18| Q0\r\n   P1 |4       17| Q1\r\n   P2 |5   74  16| Q2\r\n   P3 |6  691  15| Q3\r\n  ENP |7       14| ENT\r\n\/RRST |8       13| \/LOAD\r\n RCLK |9       12| \/OE\r\n  GND |10      11| R\/\/C\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74697\"><\/a><\/p>\n<h2>74697<\/h2>\n<p>4-bit 3-state synchronous binary up\/down counter with output registers, asynchronous reset and ripple carry output. Multiplexed register\/counter outputs.<\/p>\n<pre>      +---+--+---+\r\n U\/\/D |1  +--+ 20| VCC\r\n CCLK |2       19| RCO\r\n   P0 |3       18| Q0\r\n   P1 |4       17| Q1\r\n   P2 |5   74  16| Q2\r\n   P3 |6  697  15| Q3\r\n  ENP |7       14| ENT\r\n\/CRST |8       13| \/LOAD\r\n RCLK |9       12| \/OE\r\n  GND |10      11| R\/\/C\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74699\"><\/a><\/p>\n<h2>74699<\/h2>\n<p>4-bit 3-state synchronous binary up\/down counter with output registers, reset and ripple carry output. Multiplexed register\/counter outputs.<\/p>\n<pre>      +---+--+---+\r\n U\/\/D |1  +--+ 20| VCC\r\n CCLK |2       19| RCO\r\n   P0 |3       18| Q0\r\n   P1 |4       17| Q1\r\n   P2 |5   74  16| Q2\r\n   P3 |6  699  15| Q3\r\n  ENP |7       14| ENT\r\n\/CRST |8       13| \/LOAD\r\n RCLK |9       12| \/OE\r\n  GND |10      11| R\/\/C\r\n      +----------+<\/pre>\n<h2>74756<\/h2>\n<p>Dual 4-bit open-collector inverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+\r\n\/1OE |1  +--+ 20| VCC\r\n 1A1 |2       19| \/2OE\r\n\/2Y4 |3       18| \/1Y1\r\n 1A2 |4       17| 2A4\r\n\/2Y3 |5  74   16| \/1Y2\r\n 1A3 |6  756  15| 2A3\r\n\/2Y2 |7       14| \/1Y3\r\n 1A4 |8       13| 2A2\r\n\/2Y1 |9       12| \/1Y4\r\n GND |10      11| 2A1\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74757\"><\/a><\/p>\n<h2>74757<\/h2>\n<p>Dual 4-bit open-collector noninverting buffer\/line driver.<br \/>\nOne active low, one active high output enable.<\/p>\n<pre>     +---+--+---+\r\n\/1OE |1  +--+ 20| VCC\r\n 1A4 |2       19| 2OE\r\n 2Y1 |3       18| 1Y1\r\n 1A3 |4       17| 2A4\r\n 2Y2 |5  74   16| 1Y2\r\n 1A2 |6  757  15| 2A3\r\n 2Y3 |7       14| 1Y3\r\n 1A1 |8       13| 2A2\r\n 2Y4 |9       12| 1Y4\r\n GND |10      11| 2A1\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74758\"><\/a><\/p>\n<h2>74758<\/h2>\n<p>4-bit open-collector inverting bus transceiver.<br \/>\nTwo enable pins control output enables, one active high and one active low.<\/p>\n<pre>     +---+--+---+\r\n\/GAB |1  +--+ 14| VCC\r\n     |2       13| GBA\r\n  A1 |3  74   12|\r\n  A2 |4  758  11| B1\r\n  A3 |5       10| B2\r\n  A4 |6        9| B3\r\n GND |7        8| B4\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74760\"><\/a><\/p>\n<h2>74760<\/h2>\n<p>Dual 4-bit open-collector noninverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+\r\n\/1OE |1  +--+ 20| VCC\r\n 1A1 |2       19| \/2OE\r\n 2Y4 |3       18| 1Y1\r\n 1A2 |4       17| 2A4\r\n 2Y3 |5  74   16| 1Y2\r\n 1A3 |6  760  15| 2A3\r\n 2Y2 |7       14| 1Y3\r\n 1A4 |8       13| 2A2\r\n 2Y1 |9       12| 1Y4\r\n GND |10      11| 2A1\r\n     +----------+\r\n<\/pre>\n<h2>74804<\/h2>\n<p>Hex 2-input NAND gates\/line drivers.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n 1A |1  +--+ 20| VCC         | A | B |\/Y |      \/Y = AB\r\n 1B |2       19| 6B          +===+===*===+\r\n\/1Y |3       18| 6A          | 0 | 0 | 1 |\r\n 2A |4       17| \/6Y         | 0 | 1 | 1 |\r\n 2B |5   74  16| 5B          | 1 | 0 | 1 |\r\n\/2Y |6  804  15| 5A          | 1 | 1 | 0 |\r\n 3A |7       14| \/5Y         +---+---*---+\r\n 3B |8       13| 4B\r\n\/3Y |9       12| 4A\r\nGND |10      11| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74805\"><\/a><\/p>\n<h2>74805<\/h2>\n<p>Hex 2-input NOR gates\/line drivers.<\/p>\n<pre>    +---+--+---+             +---+---*---+           ___\r\n 1A |1  +--+ 20| VCC         | A | B |\/Y |      \/Y = A+B\r\n 1B |2       19| 6B          +===+===*===+\r\n\/1Y |3       18| 6A          | 0 | 0 | 1 |\r\n 2A |4       17| \/6Y         | 0 | 1 | 0 |\r\n 2B |5   74  16| 5B          | 1 | 0 | 0 |\r\n\/2Y |6  805  15| 5A          | 1 | 1 | 0 |\r\n 3A |7       14| \/5Y         +---+---*---+\r\n 3B |8       13| 4B\r\n\/3Y |9       12| 4A\r\nGND |10      11| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74808\"><\/a><\/p>\n<h2>74808<\/h2>\n<p>Hex 2-input AND gates\/line drivers.<\/p>\n<pre>    +---+--+---+             +---+---*---+\r\n 1A |1  +--+ 20| VCC         | A | B | Y |       Y = AB\r\n 1B |2       19| 6B          +===+===*===+\r\n 1Y |3       18| 6A          | 0 | 0 | 0 |\r\n 2A |4       17| 6Y          | 0 | 1 | 0 |\r\n 2B |5   74  16| 5B          | 1 | 0 | 0 |\r\n 2Y |6  808  15| 5A          | 1 | 1 | 1 |\r\n 3A |7       14| 5Y          +---+---*---+\r\n 3B |8       13| 4B\r\n 3Y |9       12| 4A\r\nGND |10      11| 4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74821\"><\/a><\/p>\n<h2>74821<\/h2>\n<p>10-bit 3-state D flip-flop\/bus driver.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 24| VCC         |\/OE|CLK| D | Q |\r\n D1 |2       23| Q1          +===+===+===*===+\r\n D2 |3       22| Q2          | 1 | X | X | Z |\r\n D3 |4       21| Q3          | 0 | \/ | 0 | 0 |\r\n D4 |5       20| Q4          | 0 | \/ | 1 | 1 |\r\n D5 |6   74  19| Q5          | 0 |!\/ | X | - |\r\n D6 |7  821  18| Q6          +---+---+---*---+\r\n D7 |8       17| Q7\r\n D8 |9       16| Q8\r\n D9 |10      15| Q9\r\nD10 |11      14| Q10\r\nGND |12      13| CLK\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74822\"><\/a><\/p>\n<h2>74822<\/h2>\n<p>10-bit 3-state inverting D flip-flop\/bus driver.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 24| VCC         |\/OE|CLK| D |\/Q |\r\n D1 |2       23| \/Q1         +===+===+===*===+\r\n D2 |3       22| \/Q2         | 1 | X | X | Z |\r\n D3 |4       21| \/Q3         | 0 | \/ | 0 | 1 |\r\n D4 |5       20| \/Q4         | 0 | \/ | 1 | 0 |\r\n D5 |6   74  19| \/Q5         | 0 |!\/ | X | - |\r\n D6 |7  822  18| \/Q6         +---+---+---*---+\r\n D7 |8       17| \/Q7\r\n D8 |9       16| \/Q8\r\n D9 |10      15| \/Q9\r\nD10 |11      14| \/Q10\r\nGND |12      13| CLK\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74823\"><\/a><\/p>\n<h2>74823<\/h2>\n<p>9-bit 3-state D flip-flop\/bus driver with clock enable and reset.<\/p>\n<pre>     +---+--+---+\r\n \/OE |1  +--+ 24| VCC\r\n  D1 |2       23| Q1\r\n  D2 |3       22| Q2\r\n  D3 |4       21| Q3\r\n  D4 |5       20| Q4\r\n  D5 |6   74  19| Q5\r\n  D6 |7  823  18| Q6\r\n  D7 |8       17| Q7\r\n  D8 |9       16| Q8\r\n  D9 |10      15| Q9\r\n\/RST |11      14| \/CLKEN\r\n GND |12      13| CLK\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74825\"><\/a><\/p>\n<h2>74825<\/h2>\n<p>8-bit 3-state D flip-flop\/bus driver with three output enables, clock enable and reset.<\/p>\n<pre>     +---+--+---+\r\n\/OE1 |1  +--+ 24| VCC\r\n\/OE2 |2       23| \/OE3\r\n  D1 |3       22| Q1\r\n  D2 |4       21| Q2\r\n  D3 |5       20| Q3\r\n  D4 |6   74  19| Q4\r\n  D5 |7  825  18| Q5\r\n  D6 |8       17| Q6\r\n  D7 |9       16| Q7\r\n  D8 |10      15| Q8\r\n\/RST |11      14| \/CLKEN\r\n GND |12      13| CLK\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74827\"><\/a><\/p>\n<h2>74827<\/h2>\n<p>10-bit 3-state noninverting buffer\/line driver.<\/p>\n<pre>     +---+--+---+\r\n\/OE1 |1  +--+ 24| VCC\r\n  A1 |2       23| Y1\r\n  A2 |3       22| Y2\r\n  A3 |4       21| Y3\r\n  A4 |5       20| Y4\r\n  A5 |6  742  19| Y5\r\n  A6 |7  827  18| Y6\r\n  A7 |8       17| Y7\r\n  A8 |9       16| Y8\r\n  A9 |10      15| Y9\r\n A10 |11      14| Y10\r\n GND |12      13| \/OE2\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74832\"><\/a><\/p>\n<h2>74832<\/h2>\n<p>Hex 2-input OR gates\/line drivers.<\/p>\n<pre>    +---+--+---+             +---+---*---+\r\n 1A |1  +--+ 20| VCC         | A | B | Y |       Y = A+B\r\n 1B |2       19| 6B          +===+===*===+\r\n 1Y |3       18| 6A          | 0 | 0 | 0 |\r\n 2A |4       17| 6Y          | 0 | 1 | 1 |\r\n 2B |5   74  16| 5B          | 1 | 0 | 1 |\r\n 2Y |6  832  15| 5A          | 1 | 1 | 1 |\r\n 3A |7       14| 5Y          +---+---*---+\r\n 3B |8       13| 4B\r\n 3Y |9       12| 4A\r\nGND |10      11| 4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74833\"><\/a><\/p>\n<h2>74833<\/h2>\n<p>8-bit 3-state noninverting bus transceiver with parity generator\/checker and parity register.<\/p>\n<pre>       +---+--+---+\r\n  \/OEA |1  +--+ 24| VCC\r\n    A1 |2       23| B1\r\n    A2 |3       22| B2\r\n    A3 |4       21| B3\r\n    A4 |5       20| B4\r\n    A5 |6   74  19| B5\r\n    A6 |7  833  18| B6\r\n    A7 |8       17| B7\r\n    A8 |9       16| B8\r\n\/ERROR |10      15| PAR\r\n  \/CLR |11      14| \/OEB\r\n   GND |12      13| CLK\r\n       +----------+\r\n<\/pre>\n<p><a name=\"74841\"><\/a><\/p>\n<h2>74841<\/h2>\n<p>10-bit 3-state transparent latch\/bus driver.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n\/OE |1  +--+ 24| VCC         |\/OE| LE| D | Q |\r\n D1 |2       23| Q1          +===+===+===*===+\r\n D2 |3       22| Q2          | 1 | X | X | Z |\r\n D3 |4       21| Q3          | 0 | 0 | X | - |\r\n D4 |5       20| Q4          | 0 | 1 | 0 | 0 |\r\n D5 |6   74  19| Q5          | 0 | 1 | 1 | 1 |\r\n D6 |7  841  18| Q6          +---+---+---*---+\r\n D7 |8       17| Q7\r\n D8 |9       16| Q8\r\n D9 |10      15| Q9\r\nD10 |11      14| Q10\r\nGND |12      13| LE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74843\"><\/a><\/p>\n<h2>74843<\/h2>\n<p>9-bit 3-state transparent latch\/bus driver with set and reset.<\/p>\n<pre>     +---+--+---+            +----+----+---+---+---*---+\r\n \/OE |1  +--+ 24| VCC        |\/RST|\/SET|\/OE| LE| D | Q |\r\n  D1 |2       23| Q1         +====+====+===+===+===*===+\r\n  D2 |3       22| Q2         |  0 |  1 | 0 | X | X | 0 |\r\n  D3 |4       21| Q3         |  1 |  0 | 0 | X | X | 0 |\r\n  D4 |5       20| Q4         |  X |  X | 1 | X | X | Z |\r\n  D5 |6   74  19| Q5         |  1 |  1 | 0 | 0 | X | - |\r\n  D6 |7  843  18| Q6         |  1 |  1 | 0 | 1 | 0 | 0 |\r\n  D7 |8       17| Q7         |  1 |  1 | 0 | 1 | 1 | 1 |\r\n  D8 |9       16| Q8         +----+----+---+---+---*---+\r\n  D9 |10      15| Q9\r\n\/RST |11      14| \/SET\r\n GND |12      13| LE\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74845\"><\/a><\/p>\n<h2>74845<\/h2>\n<p>8-bit 3-state transparent latch\/bus driver with three output enables, set and reset.<\/p>\n<pre>     +---+--+---+\r\n\/OE1 |1  +--+ 24| VCC\r\n\/OE2 |2       23| \/OE3\r\n  D1 |3       22| Q1\r\n  D2 |4       21| Q2\r\n  D3 |5       20| Q3\r\n  D4 |6   74  19| Q4\r\n  D5 |7  845  18| Q5\r\n  D6 |8       17| Q6\r\n  D7 |9       16| Q7\r\n  D8 |10      15| Q8\r\n\/RST |11      14| \/SET\r\n GND |12      13| LE\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74857\"><\/a><\/p>\n<h2>74857<\/h2>\n<p>12-to-6 line inverting\/noninverting data selector\/multiplexer with masking and zero detect.<\/p>\n<pre>      +---+--+---+\r\n   S0 |1  +--+ 24| VCC\r\n  1A0 |2       23| S1\r\n  1A1 |3       22| 6A0\r\n   1Y |4       21| 6A1\r\n  2A0 |5       20| 6Y\r\n  2A1 |6   74  19| 5A0\r\n   2Y |7  857  18| 5A1\r\n  3A0 |8       17| 5Y\r\n  3A1 |9       16| 4A0\r\n   3Y |10      15| 4A1\r\n   ZD |11      14| 4Y\r\n  GND |12      13| COMP\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74861\"><\/a><\/p>\n<h2>74861<\/h2>\n<p>10-bit 3-state noninverting bus transceiver.<\/p>\n<pre>     +---+--+---+\r\n\/GBA |1  +--+ 24| VCC\r\n  A1 |2       23| B1\r\n  A2 |3       22| B2\r\n  A3 |4       21| B3\r\n  A4 |5       20| B4\r\n  A5 |6   74  19| B5\r\n  A6 |7  861  18| B6\r\n  A7 |8       17| B7\r\n  A8 |9       16| B8\r\n  A9 |10      15| B9\r\n A10 |11      14| B10\r\n GND |12      13| \/GAB\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74863\"><\/a><\/p>\n<h2>74863<\/h2>\n<p>9-bit 3-state noninverting bus transceiver.<\/p>\n<pre>      +---+--+---+\r\n\/GBA1 |1  +--+ 24| VCC\r\n   A1 |2       23| B1\r\n   A2 |3       22| B2\r\n   A3 |4       21| B3\r\n   A4 |5       20| B4\r\n   A5 |6   74  19| B5\r\n   A6 |7  863  18| B6\r\n   A7 |8       17| B7\r\n   A8 |9       16| B8\r\n   A9 |10      15| B9\r\n\/GBA2 |11      14| \/GAB2\r\n  GND |12      13| \/GAB1\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74867\"><\/a><\/p>\n<h2>74867<\/h2>\n<p>8-bit synchronous binary up\/down counter with load, asynchronous reset and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\n  S0 |1  +--+ 24| VCC\r\n  S1 |2       23| \/ENP\r\n  P0 |3       22| Q0\r\n  P1 |4       21| Q1\r\n  P2 |5       20| Q2\r\n  P3 |6   74  19| Q3\r\n  P4 |7  867  18| Q4\r\n  P5 |8       17| Q5\r\n  P6 |9       16| Q6\r\n  P7 |10      15| Q7\r\n\/ENT |11      14| CLK\r\n GND |12      13| \/RCO\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74869\"><\/a><\/p>\n<h2>74869<\/h2>\n<p>8-bit synchronous binary up\/down counter with load, reset and ripple carry output.<\/p>\n<pre>     +---+--+---+\r\n  S0 |1  +--+ 24| VCC\r\n  S1 |2       23| \/ENP\r\n  P0 |3       22| Q0\r\n  P1 |4       21| Q1\r\n  P2 |5       20| Q2\r\n  P3 |6   74  19| Q3\r\n  P4 |7  869  18| Q4\r\n  P5 |8       17| Q5\r\n  P6 |9       16| Q6\r\n  P7 |10      15| Q7\r\n\/ENT |11      14| CLK\r\n GND |12      13| \/RCO\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74873\"><\/a><\/p>\n<h2>74873<\/h2>\n<p>Dual 4-bit 3-state transparent latch with reset.<\/p>\n<pre>      +---+--+---+\r\n\/1RST |1  +--+ 24| VCC\r\n \/1OE |2       23| 1LE\r\n  1D1 |3       22| 1Q1\r\n  1D2 |4       21| 1Q2\r\n  1D3 |5       20| 1Q3\r\n  1D4 |6   74  19| 1Q4\r\n  2D1 |7  873  18| 2Q1\r\n  2D2 |8       17| 2Q2\r\n  2D3 |9       16| 2Q3\r\n  2D4 |10      15| 2Q4\r\n \/2OE |11      14| 2LE\r\n  GND |12      13| \/2RST\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74874\"><\/a><\/p>\n<h2>74874<\/h2>\n<p>Dual 4-bit 3-state D flip-flops with reset.<\/p>\n<pre>      +---+--+---+           +----+---+---+---*---+\r\n\/1RST |1  +--+ 24| VCC       |\/RST|\/OE|CLK| D | Q |\r\n \/1OE |2       23| 1CLK      +====+===+===+===*===+\r\n  1D1 |3       22| 1Q1       |  0 | 1 | X | X | Z |\r\n  1D2 |4       21| 1Q2       |  X | 0 | X | X | 0 |\r\n  1D3 |5       20| 1Q3       |  1 | 0 | \/ | 0 | 0 |\r\n  1D4 |6   74  19| 1Q4       |  1 | 0 | \/ | 1 | 1 |\r\n  2D1 |7  874  18| 2Q1       |  1 | 0 |!\/ | X | - |\r\n  2D2 |8       17| 2Q2       +----+---+---+---*---+\r\n  2D3 |9       16| 2Q3\r\n  2D4 |10      15| 2Q4\r\n \/2OE |11      14| 2CLK\r\n  GND |12      13| \/2RST\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74878\"><\/a><\/p>\n<h2>74878<\/h2>\n<p>Dual 4-bit 3-state D flip-flops with reset.<\/p>\n<pre>      +---+--+---+           +----+---+---+---*---+\r\n\/1RST |1  +--+ 24| VCC       |\/RST|\/OE|CLK| D | Q |\r\n \/1OE |2       23| 1CLK      +====+===+===+===*===+\r\n  1D1 |3       22| 1Q1       |  0 | 1 | X | X | Z |\r\n  1D2 |4       21| 1Q2       |  X | 0 | X | X | 0 |\r\n  1D3 |5       20| 1Q3       |  1 | 0 | \/ | 0 | 0 |\r\n  1D4 |6   74  19| 1Q4       |  1 | 0 | \/ | 1 | 1 |\r\n  2D1 |7  878  18| 2Q1       |  1 | 0 |!\/ | X | - |\r\n  2D2 |8       17| 2Q2       +----+---+---+---*---+\r\n  2D3 |9       16| 2Q3\r\n  2D4 |10      15| 2Q4\r\n \/2OE |11      14| 2CLK\r\n  GND |12      13| \/2RST\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74881\"><\/a><\/p>\n<h2>74881<\/h2>\n<p>4-bit 16-function arithmetic logic unit (ALU)<\/p>\n<pre>    +---+--+---+\r\n\/B0 |1  +--+ 24| VCC\r\n\/A0 |2       23| \/A1\r\n S3 |3       22| \/B1\r\n S2 |4       21| \/A2\r\n S1 |5       20| \/B2\r\n S0 |6   74  19| \/A3\r\nCIN |7  881  18| \/B3\r\n  M |8       17| \/G\r\n\/F0 |9       16| COUT\r\n\/F1 |10      15| \/P\r\n\/F2 |11      14| A=B\r\nGND |12      13| \/F3\r\n    +----------+\r\n<\/pre>\n<p><a name=\"74885\"><\/a><\/p>\n<h2>74885<\/h2>\n<p>8-bit noninverting magnitude comparator with cascade inputs and latchable A inputs.<\/p>\n<pre>     +---+--+---+\r\nL+\/A |1  +--+ 24| VCC\r\nIA&lt;B |2       23| ALE\r\nIA&gt;B |3       22| A7\r\n  B7 |4       21| A6\r\n  B6 |5       20| A5\r\n  B5 |6   74  19| A4\r\n  B4 |7  885  18| A3\r\n  B3 |8       17| A2\r\n  B2 |9       16| A1\r\n  B1 |10      15| A0\r\n  B0 |11      14| OA&lt;B\r\n GND |12      13| OA&gt;B\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74899\"><\/a><\/p>\n<h2>74899<\/h2>\n<p>8-bit 3-state noninverting latchable bus transceiver with parity generator\/checker and independent latch-enable inputs.<\/p>\n<pre>      +---+--+---+\r\n O\/\/E |1  +--+ 28| VCC\r\n\/ERRA |2       27| \/OEAB\r\n LEAB |3       26| B1\r\n   A1 |4       25| B2\r\n   A2 |5       24| B3\r\n   A3 |6       23| B4\r\n   A4 |7   74  22| B5\r\n   A5 |8  899  21| B6\r\n   A6 |9       20| B7\r\n   A7 |10      19| B8\r\n   A8 |11      18| BPAR\r\n APAR |12      17| LEBA\r\n\/OEBA |13      16| \/SEL\r\n  GND |14      15| \/ERRB\r\n      +----------+\r\n<\/pre>\n<h2>74956<\/h2>\n<p>8-bit 3-state noninverting latched transceiver.<\/p>\n<pre>     +---+--+---+\r\nLEAB |1  +--+ 24| VCC\r\n SAB |2       23| LEBA\r\n DIR |3       22| SBA\r\n  A1 |4       21| \/OE\r\n  A2 |5       20| B1\r\n  A3 |6   74  19| B2\r\n  A4 |7  956  18| B3\r\n  A5 |8       17| B4\r\n  A6 |9       16| B5\r\n  A7 |10      15| B6\r\n  A8 |11      14| B7\r\n GND |12      13| B8\r\n     +----------+\r\n<\/pre>\n<p><a name=\"74990\"><\/a><\/p>\n<h2>74990<\/h2>\n<p>8-bit transparent latch with readback.<\/p>\n<pre>      +---+--+---+\r\n\/OERB |1  +--+ 20| VCC\r\n   D1 |2       19| Q1\r\n   D2 |3       18| Q2\r\n   D3 |4       17| Q3\r\n   D4 |5   74  16| Q4\r\n   D5 |6  990  15| Q5\r\n   D6 |7       14| Q6\r\n   D7 |8       13| Q7\r\n   D8 |9       12| Q8\r\n  GND |10      11| LE\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74992\"><\/a><\/p>\n<h2>74992<\/h2>\n<p>9-bit 3-state transparent latch with readback and reset.<\/p>\n<pre>      +---+--+---+\r\n\/OERB |1  +--+ 24| VCC\r\n   D1 |2       23| Q1\r\n   D2 |3       22| Q2\r\n   D3 |4       21| Q3\r\n   D4 |5       20| Q4\r\n   D5 |6   74  19| Q5\r\n   D6 |7  992  18| Q6\r\n   D7 |8       17| Q7\r\n   D8 |9       16| Q8\r\n   D9 |10      15| Q9\r\n \/RST |11      14| \/OE\r\n  GND |12      13| LE\r\n      +----------+\r\n<\/pre>\n<p><a name=\"74994\"><\/a><\/p>\n<h2>74994<\/h2>\n<p>10-bit transparent latch with readback.<\/p>\n<pre>      +---+--+---+\r\n\/OERB |1  +--+ 24| VCC\r\n   D1 |2       23| Q1\r\n   D2 |3       22| Q2\r\n   D3 |4       21| Q3\r\n   D4 |5       20| Q4\r\n   D5 |6   74  19| Q5\r\n   D6 |7  994  18| Q6\r\n   D7 |8       17| Q7\r\n   D8 |9       16| Q8\r\n   D9 |10      15| Q9\r\n  D10 |11      14| Q10\r\n  GND |12      13| LE\r\n      +----------+<\/pre>\n<h2>741000<\/h2>\n<p>Quad 2-input NAND gates with buffered output.<\/p>\n<pre>    +---+--+---+             +---+---*---+           __\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |      \/Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3  7410 12| 4A          | 0 | 0 | 1 |\r\n 2A |4   00  11| \/4Y         | 0 | 1 | 1 |\r\n 2B |5       10| 3B          | 1 | 0 | 1 |\r\n\/2Y |6        9| 3A          | 1 | 1 | 0 |\r\nGND |7        8| \/3Y         +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"741004\"><\/a><\/p>\n<h2>741004<\/h2>\n<p>Hex inverters with buffered output.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\n 1A |1  +--+ 14| VCC         | A |\/Y |          \/Y = A\r\n\/1Y |2       13| 6A          +===*===+\r\n 2A |3  7410 12| \/6Y         | 0 | Z |\r\n\/2Y |4   04  11| 5A          | 1 | 0 |\r\n 3A |5       10| \/5Y         +---*---+\r\n\/3Y |6        9| 4A\r\nGND |7        8| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"741005\"><\/a><\/p>\n<h2>741005<\/h2>\n<p>Hex open-collector inverters with buffered output.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\n 1A |1  +--+ 14| VCC         | A |\/Y |          \/Y = A\r\n\/1Y |2       13| 6A          +===*===+\r\n 2A |3  7410 12| \/6Y         | 0 | Z |\r\n\/2Y |4   05  11| 5A          | 1 | 0 |\r\n 3A |5       10| \/5Y         +---*---+\r\n\/3Y |6        9| 4A\r\nGND |7        8| \/4Y\r\n    +----------+\r\n<\/pre>\n<p><a name=\"741032\"><\/a><\/p>\n<h2>741032<\/h2>\n<p>Quad 2-input OR gates with buffered output.<\/p>\n<pre>    +---+--+---+             +---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | Y |       Y = A+B\r\n 1B |2       13| 4B          +===+===*===+\r\n 1Y |3  7410 12| 4A          | 0 | 0 | 0 |\r\n 2A |4   32  11| 4Y          | 0 | 1 | 1 |\r\n 2B |5       10| 3B          | 1 | 0 | 1 |\r\n 2Y |6        9| 3A          | 1 | 1 | 1 |\r\nGND |7        8| 3Y          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"743351\"><\/a><\/p>\n<h2>743351<\/h2>\n<p>10-tap noninverting delay lines (20, 50 or 100ns total delay).<\/p>\n<pre>    +---+--+---+\r\n  A |1  +--+ 16| VCC\r\n    |2       15|\r\n    |3       14| Y1\r\n Y2 |4  743  13| Y3\r\n Y4 |5  351  12| Y5\r\n Y6 |6       11| Y7\r\n Y8 |7       10| Y9\r\nGND |8        9| Y10\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744374\"><\/a><\/p>\n<h2>744374<\/h2>\n<p>8-bit 3-state dual-ranking D flip flop.<br \/>\nDesigned to prevent metastable conditions in data synchronization applications in which setup and hold times may be violated.<\/p>\n<pre>    +---+--+---+\r\n Q1 |1  +--+ 20| D1\r\n Q2 |2       19| D2\r\n Q3 |3       18| D3\r\n Q4 |4       17| D4\r\nGND |5  744  16| VCC\r\n Q5 |6  374  15| D5\r\n Q6 |7       14| D6\r\n Q7 |8       13| D7\r\n Q8 |9       12| D8\r\n\/OE |10      11| CLK\r\n    +----------+\r\n<\/pre>\n<p><a name=\"747001\"><\/a><\/p>\n<h2>747001<\/h2>\n<p>Quad 2-input AND gates with schmitt-trigger inputs.<br \/>\n0.8V typical input hysteresis at VCC=+5V.<\/p>\n<pre>    +---+--+---+             +---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | Y |       Y = AB\r\n 1B |2       13| 4B          +===+===*===+\r\n 1Y |3  747  12| 4A          | 0 | 0 | 0 |\r\n 2A |4  001  11| 4Y          | 0 | 1 | 0 |\r\n 2B |5       10| 3B          | 1 | 0 | 0 |\r\n 2Y |6        9| 3A          | 1 | 1 | 1 |\r\nGND |7        8| 3Y          +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"747266\"><\/a><\/p>\n<h2>747266<\/h2>\n<p>Quad 2-input XNOR gates.<\/p>\n<pre>    +---+--+---+             +---+---*---+          _     _ _\r\n 1A |1  +--+ 14| VCC         | A | B |\/Y |     Y = A$B = (A.B)+(A.B)\r\n 1B |2       13| 4B          +===+===*===+\r\n\/1Y |3  747  12| 4A          | 0 | 0 | 1 |\r\n 2A |4  266  11| \/4Y         | 0 | 1 | 0 |\r\n 2B |5       10| 3B          | 1 | 0 | 0 |\r\n\/2Y |6        9| 3A          | 1 | 1 | 1 |\r\nGND |7        8| \/3Y         +---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"748003\"><\/a><\/p>\n<h2>748003<\/h2>\n<p>Dual 2-input NAND gates.<\/p>\n<pre>    +---+--+---+                 __\r\n 1A |1  +--+  8| VCC        \/Y = AB\r\n 1B |2  748   7| 2B\r\n\/1Y |3  003   6| 2A\r\nGND |4        5| \/2Y\r\n    +----------+\r\n<\/pre>\n<h2>744002<\/h2>\n<p>Dual 4-input NOR gates.<\/p>\n<pre>    +---+--+---+             +---+---+---+---*---+       _________\r\n\/1Y |1  +--+ 14| VCC         | A | B | C | D |\/Y |  \/Y = (A+B+C+D)\r\n 1A |2       13| \/2Y         +===+===+===+===*===+\r\n 1B |3       12| 2D          | 0 | 0 | 0 | 0 | 1 |\r\n 1C |4  4002 11| 2C          | 0 | 0 | 0 | 1 | 0 |\r\n 1D |5       10| 2B          | 0 | 0 | 1 | X | 0 |\r\n    |6        9| 2A          | 0 | 1 | X | X | 0 |\r\nGND |7        8|             | 1 | X | X | X | 0 |\r\n    +----------+             +---+---+---+---*---+\r\n<\/pre>\n<p><a name=\"744015\"><\/a><\/p>\n<h2>744015<\/h2>\n<p>Dual 4-bit serial-in parallel-out shift register with asynchronous reset.<\/p>\n<pre>     +---+--+---+\r\n2CLK |1  +--+ 16| VCC\r\n 2Q3 |2       15| 2D\r\n 1Q2 |3       14| 2RST\r\n 1Q1 |4       13| 2Q0\r\n 1Q0 |5  4015 12| 2Q1\r\n1RST |6       11| 2Q2\r\n  1D |7       10| 1Q3\r\n GND |8        9| 1CLK\r\n     +----------+\r\n<\/pre>\n<p><a name=\"744016\"><\/a><\/p>\n<h2>744016<\/h2>\n<p>Quad analog switches.<\/p>\n<pre>     +---+--+---+\r\n  1X |1  +--+ 14| VCC\r\n  1Y |2       13| 1EN\r\n  2Y |3       12| 4EN\r\n  2X |4  4016 11| 4X\r\n 2EN |5  4066 10| 4Y\r\n 3EN |6        9| 3Y\r\n GND |7        8| 3X\r\n     +----------+\r\n<\/pre>\n<p><a name=\"744017\"><\/a><\/p>\n<h2>744017<\/h2>\n<p>4-bit asynchronous decade counter with fully decoded outputs, reset and both active high and active low clocks.<\/p>\n<pre>    +---+--+---+\r\n Q5 |1  +--+ 16| VCC\r\n Q1 |2       15| RST\r\n Q0 |3       14| CLK1\r\n Q2 |4       13| \/CLK2\r\n Q6 |5  4017 12| RCO\r\n Q7 |6       11| Q9\r\n Q3 |7       10| Q4\r\nGND |8        9| Q8\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744020\"><\/a><\/p>\n<h2>744020<\/h2>\n<p>14-bit asynchronous binary counter with reset.<br \/>\nQ1 and Q2 outputs missing.<\/p>\n<pre>    +---+--+---+\r\nQ11 |1  +--+ 16| VCC\r\nQ12 |2       15| Q10\r\nQ13 |3       14| Q9\r\n Q5 |4       13| Q7\r\n Q4 |5  4020 12| Q8\r\n Q6 |6       11| RST\r\n Q3 |7       10| \/CLK\r\nGND |8        9| Q0\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744024\"><\/a><\/p>\n<h2>744024<\/h2>\n<p>7-bit asynchronous binary counter with reset.<\/p>\n<pre>     +---+--+---+\r\n\/CLK |1  +--+ 14| VCC\r\n RST |2       13|\r\n  Q6 |3       12| Q0\r\n  Q5 |4  4024 11| Q1\r\n  Q4 |5       10|\r\n  Q3 |6        9| Q2\r\n GND |7        8|\r\n     +----------+\r\n<\/pre>\n<p><a name=\"744040\"><\/a><\/p>\n<h2>744040<\/h2>\n<p>12-bit asynchronous binary counter with reset.<\/p>\n<pre>    +---+--+---+\r\nQ11 |1  +--+ 16| VCC\r\n Q5 |2       15| Q10\r\n Q4 |3       14| Q9\r\n Q6 |4       13| Q7\r\n Q3 |5  4040 12| Q8\r\n Q2 |6       11| RST\r\n Q1 |7       10| \/CLK\r\nGND |8        9| Q0\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744046\"><\/a><\/p>\n<h2>744046<\/h2>\n<p>Phase Locked Loop.<\/p>\n<pre>       +---+--+---+\r\nPCPout |1  +--+ 16| VCC\r\nPC1out |2       15| Zener\r\n PCinB |3       14| PCinA\r\nVCOout |4       13| PC2out\r\n   \/EN |5  4046 12| R2\r\n   C1A |6       11| R1\r\n   C1B |7       10| SFout\r\n   GND |8        9| VCOin\r\n       +----------+\r\n<\/pre>\n<p><a name=\"744049\"><\/a><\/p>\n<h2>744049<\/h2>\n<p>Hex inverters with high-to-low level shifter inputs.<\/p>\n<pre>    +---+--+---+             +---*---+               _\r\nVCC |1  +--+ 16|             | A |\/Y |          \/Y = A\r\n\/Y1 |2       15| \/Y6         +===*===+\r\n A1 |3       14| A6          | 0 | 1 |\r\n\/Y2 |4       13|             | 1 | 0 |\r\n A2 |5  4049 12| \/Y5         +---*---+\r\n\/Y3 |6       11| A5\r\n A3 |7       10| \/Y4\r\nGND |8        9| A4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744050\"><\/a><\/p>\n<h2>744050<\/h2>\n<p>Hex buffers with high-to-low level shifter inputs.<\/p>\n<pre>    +---+--+---+             +---*---+\r\nVCC |1  +--+ 16|             | A | Y |           Y = A\r\n Y1 |2       15| Y6          +===*===+\r\n A1 |3       14| A6          | 0 | 0 |\r\n Y2 |4       13|             | 1 | 1 |\r\n A2 |5  4050 12| Y5          +---*---+\r\n Y3 |6       11| A5\r\n A3 |7       10| Y4\r\nGND |8        9| A4\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744051\"><\/a><\/p>\n<h2>744051<\/h2>\n<p>8-to-1 line analog multiplexer\/demultiplexer with dual power supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+--+---+\r\n X4 |1  +--+ 16| VCC\r\n X6 |2       15| X2\r\n  Y |3       14| X1\r\n X7 |4       13| X0\r\n X5 |5  4051 12| X3\r\n\/EN |6       11| S0\r\nVEE |7       10| S1\r\nGND |8        9| S2\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744052\"><\/a><\/p>\n<h2>744052<\/h2>\n<p>8-to-2 line analog multiplexer\/demultiplexer with dual power supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+--+---+\r\n1X0 |1  +--+ 16| VCC\r\n1X2 |2       15| 2X2\r\n 1Y |3       14| 2X1\r\n1X3 |4       13| 2Y\r\n1X1 |5  4052 12| 2X0\r\n\/EN |6       11| 2X3\r\nVEE |7       10| S0\r\nGND |8        9| S1\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744053\"><\/a><\/p>\n<h2>744053<\/h2>\n<p>Triple 2-to-1 line analog multiplexer\/demultiplexer with dual power supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+--+---+\r\n1X0 |1  +--+ 16| VCC\r\n1X1 |2       15| 1Y\r\n2X1 |3       14| 3Y\r\n 2Y |4       13| 3X1\r\n2X0 |5  4053 12| 3X0\r\n\/EN |6       11| 3S\r\nVEE |7       10| 1S\r\nGND |8        9| 2S\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744060\"><\/a><\/p>\n<h2>744060<\/h2>\n<p>14-bit asynchronous binary counter with oscillator and reset input.<br \/>\nQ0,Q1,Q2 and Q10 outputs are missing.<\/p>\n<pre>    +---+--+---+\r\nQ11 |1  +--+ 16| VCC\r\nQ12 |2       15| Q9\r\nQ13 |3       14| Q7\r\n Q5 |4       13| Q8\r\n Q4 |5  4060 12| RST\r\n Q6 |6       11| X1\r\n Q3 |7       10| X0\r\nGND |8        9| X2\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744066\"><\/a><\/p>\n<h2>744066<\/h2>\n<p>Quad analog switches.<\/p>\n<pre>     +---+--+---+\r\n  1X |1  +--+ 14| VCC\r\n  1Y |2       13| 1EN\r\n  2Y |3       12| 4EN\r\n  2X |4  4016 11| 4X\r\n 2EN |5  4066 10| 4Y\r\n 3EN |6        9| 3Y\r\n GND |7        8| 3X\r\n     +----------+\r\n<\/pre>\n<p><a name=\"744067\"><\/a><\/p>\n<h2>744067<\/h2>\n<p>16-to-1 line analog multiplexer\/demultiplexer.<\/p>\n<pre>    +-----+--+-----+\r\n  Y |1    +--+   24| VCC\r\n X7 |2           23| X8\r\n X6 |3           22| X9\r\n X5 |4           21| X10\r\n X4 |5           20| X11\r\n X3 |6           19| X12\r\n X2 |7    4067   18| X13\r\n X1 |8           17| X14\r\n X0 |9           16| X15\r\n S0 |10          15| \/EN\r\n S1 |11          14| S2\r\nGND |12          13| S3\r\n    +--------------+\r\n<\/pre>\n<p><a name=\"744075\"><\/a><\/p>\n<h2>744075<\/h2>\n<p>Triple 3-input OR gates.<\/p>\n<pre>    +---+--+---+             +---+---+---*---+\r\n 1A |1  +--+ 14| VCC         | A | B | C | Y |   Y = A+B+C\r\n 1B |2       13| 3A          +===+===+===*===+\r\n 2A |3       12| 3B          | 0 | 0 | 0 | 0 |\r\n 2B |4  4075 11| 3C          | 0 | 0 | 1 | 1 |\r\n 2C |5       10| 3Y          | 0 | 1 | X | 1 |\r\n 2Y |6        9| 1Y          | 1 | X | X | 1 |\r\nGND |7        8| 1C          +---+---+---*---+\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744078\"><\/a><\/p>\n<h2>744078<\/h2>\n<p>8-input OR\/NOR gate with complementary outputs.<\/p>\n<pre>    +---+--+---+\r\n  Y |1  +--+ 14| VCC         Y=A+B+C+D+E+F+G+H\r\n  A |2       13| \/Y\r\n  B |3       12| H\r\n  C |4  4078 11| G\r\n  D |5       10| F\r\n    |6        9| E\r\nGND |7        8|\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744316\"><\/a><\/p>\n<h2>744316<\/h2>\n<p>Quad analog switches with enable input and dual power supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+--+---+\r\n 1X |1  +--+ 16| VCC\r\n 1Y |2       15| 1EN\r\n 2Y |3       14| 4EN\r\n 2X |4       13| 4X\r\n2EN |5  4316 12| 4Y\r\n3EN |6       11| 3Y\r\n EN |7       10| 3X\r\nGND |8        9| VEE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744351\"><\/a><\/p>\n<h2>744351<\/h2>\n<p>8-to-1 line analog multiplexer\/demultiplexer with address latch and dual power supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+--+---+\r\n1X0 |1  +--+ 18| VCC\r\n1X1 |2       17| X2\r\n2X1 |3       16| X1\r\n 2Y |4       15| X0\r\n2X0 |5  4351 14| X3\r\n\/EN |6       13| S0\r\n EN |7       12| S1\r\nVEE |8       11| S2\r\nGND |9       10| LE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744352\"><\/a><\/p>\n<h2>744352<\/h2>\n<p>8-to-2 line analog multiplexer\/demultiplexer with address latch and dual power supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+--+---+\r\n1X0 |1  +--+ 18| VCC\r\n1X2 |2       17| 2X2\r\n 1Y |3       16| 2X1\r\n1X3 |4       15| 2Y\r\n1X1 |5  4352 14| 2X0\r\n\/EN |6       13| 2X3\r\n EN |7       12| S0\r\nVEE |8       11| S1\r\nGND |9       10| LE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744353\"><\/a><\/p>\n<h2>744353<\/h2>\n<p>Triple 2-to-1 line analog multiplexer\/demultiplexer with address latch and dual power supply.<br \/>\nVEE supply may not be more positive than GND.<\/p>\n<pre>    +---+--+---+\r\n1X0 |1  +--+ 18| VCC\r\n1X1 |2       17| 1Y\r\n2X1 |3       16| 3Y\r\n 2Y |4       15| 3X1\r\n2X0 |5  4353 14| 3X0\r\n\/EN |6       13| 3S\r\n EN |7       12| 1S\r\nVEE |8       11| 2S\r\nGND |9       10| LE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744511\"><\/a><\/p>\n<h2>744511<\/h2>\n<p>BCD to 7-segment decoder\/common-cathode LED driver.<\/p>\n<pre>    +---+--+---+\r\n A1 |1  +--+ 16| VCC\r\n A2 |2       15| YF\r\n\/LT |3       14| YG\r\n\/BI |4       13| YA\r\n\/LE |5  4511 12| YB\r\n A3 |6       11| YC\r\n A0 |7       10| YD\r\nGND |8        9| YE\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744514\"><\/a><\/p>\n<h2>744514<\/h2>\n<p>1-of-16 noninverting decoder\/demultiplexer with address latches.<\/p>\n<pre>    +---+--+---+\r\n LE |1  +--+ 24| VCC\r\n S0 |2       23| \/EN\r\n S1 |3       22| S3\r\n Y7 |4       21| S2\r\n Y6 |5       20| Y10\r\n Y5 |6       19| Y11\r\n Y4 |7  4514 18| Y8\r\n Y3 |8       17| Y9\r\n Y2 |9       16| Y15\r\n Y1 |10      15| Y14\r\n Y0 |11      14| Y13\r\nGND |12      13| Y12\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744515\"><\/a><\/p>\n<h2>744515<\/h2>\n<p>1-of-16 inverting decoder\/demultiplexer with address latches.<\/p>\n<pre>    +---+--+---+\r\n LE |1  +--+ 24| VCC\r\n S0 |2       23| \/EN\r\n S1 |3       22| S3\r\n\/Y7 |4       21| S2\r\n\/Y6 |5       20| \/Y10\r\n\/Y5 |6       19| \/Y11\r\n\/Y4 |7  4515 18| \/Y8\r\n\/Y3 |8       17| \/Y9\r\n\/Y1 |9       16| \/Y15\r\n\/Y2 |10      15| \/Y14\r\n\/Y0 |11      14| \/Y12\r\nGND |12      13| \/Y13\r\n    +----------+\r\n<\/pre>\n<p><a name=\"744518\"><\/a><\/p>\n<h2>744518<\/h2>\n<p>Dual 4-bit asynchronous decade counters with reset and both active high and active low clocks.<\/p>\n<pre>      +---+--+---+\r\n 1CLK |1  +--+ 16| VCC\r\n\/1CLK |2       15| 2RST\r\n  1Q0 |3       14| 2Q3\r\n  1Q1 |4       13| 2Q2\r\n  1Q2 |5  4518 12| 2Q1\r\n  1Q3 |6       11| 2Q0\r\n 1RST |7       10| \/2CLK\r\n  GND |8        9| 2CLK\r\n      +----------+\r\n<\/pre>\n<p><a name=\"744520\"><\/a><\/p>\n<h2>744520<\/h2>\n<p>Dual 4-bit asynchronous binary counters with reset and both active high and active low clocks.<\/p>\n<pre>      +---+--+---+\r\n 1CLK |1  +--+ 16| VCC\r\n\/1CLK |2       15| 2RST\r\n  1Q0 |3       14| 2Q3\r\n  1Q1 |4       13| 2Q2\r\n  1Q2 |5  4520 12| 2Q1\r\n  1Q3 |6       11| 2Q0\r\n 1RST |7       10| \/2CLK\r\n  GND |8        9| 2CLK\r\n      +----------+\r\n<\/pre>\n<p><a name=\"744538\"><\/a><\/p>\n<h2>744538<\/h2>\n<p>Dual precision monostable multivibrator with Schmitt-trigger inputs.<br \/>\nRetriggerable, resettable. For 74HC4538 the Cext pins may be grounded.<\/p>\n<pre>       +---+--+---+\r\n 1Cext |1  +--+ 16| VCC\r\n1RCext |2       15| 2Cext\r\n  1RST |3       14| 2RCext\r\n   1TR |4       13| 2RST\r\n  \/1TR |5  4538 12| 2TR\r\n    1Q |6       11| \/2TR\r\n   \/1Q |7       10| 2Q\r\n   GND |8        9| \/2Q\r\n       +----------+\r\n<\/pre>\n<p><a name=\"744543\"><\/a><\/p>\n<h2>744543<\/h2>\n<p>BCD to 7-segment decoder\/LCD driver with input latch.<br \/>\nThe P (phase) input should be connected to the backplane of the LCD.<\/p>\n<pre>    +---+--+---+\r\n LE |1  +--+ 16| VCC\r\n A2 |2       15| YF\r\n A1 |3       14| YG\r\n A3 |4       13| YE\r\n A0 |5  4543 12| YD\r\n  P |6       11| YC\r\n BI |7       10| YB\r\nGND |8        9| YA\r\n    +----------+\r\n<\/pre>\n<p><a name=\"7440102\"><\/a><\/p>\n<h2>7440102<\/h2>\n<p>8-bit (2-digit) synchronous decade down counter with synchronous and asynchronous load and reset. Counter outputs only internally connected but ripple carry and zero detect outputs available.<\/p>\n<pre>       +---+--+---+\r\n   CLK |1  +--+ 16| VCC\r\n  \/RST |2       15| \/SLD\r\n\/CLKEN |3       14| \/RCO\r\n    P0 |4       13| P7\r\n    P1 |5 40102 12| P6\r\n    P2 |6       11| P5\r\n    P3 |7       10| P4\r\n   GND |8        9| \/ALD\r\n       +----------+\r\n<\/pre>\n<p><a name=\"7440103\"><\/a><\/p>\n<h2>7440103<\/h2>\n<p>8-bit synchronous binary down counter with synchronous and asynchronous load and reset. Counter outputs only internally connected but ripple carry and zero detect outputs available.<\/p>\n<pre>       +---+--+---+\r\n   CLK |1  +--+ 16| VCC\r\n  \/RST |2       15| \/SLD\r\n\/CLKEN |3       14| \/RCO\r\n    P0 |4       13| P7\r\n    P1 |5 40103 12| P6\r\n    P2 |6       11| P5\r\n    P3 |7       10| P4\r\n   GND |8        9| \/ALD\r\n       +----------+<\/pre>\n","protected":false},"excerpt":{"rendered":"<p>7400 series TTL IC&#8217;s 7400 Quad 2-input NAND gates. +&#8212;+&#8211;+&#8212;+ +&#8212;+&#8212;*&#8212;+ __ 1A |1 +&#8211;+ 14| VCC | A | B |\/Y | \/Y = AB 1B |2 13| 4B +===+===*===+ \/1Y |3 12| 4A | 0 | 0 | 1 | 2A |4 7400 11| \/4Y | 0 | 1 | 1 | 2B &hellip; <\/p>\n<p class=\"link-more\"><a href=\"https:\/\/pcbjunkie.net\/index.php\/resources\/74-series-ics\/\" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;74 Series ICs&#8221;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":277,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-295","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/pages\/295","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/comments?post=295"}],"version-history":[{"count":1,"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/pages\/295\/revisions"}],"predecessor-version":[{"id":296,"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/pages\/295\/revisions\/296"}],"up":[{"embeddable":true,"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/pages\/277"}],"wp:attachment":[{"href":"https:\/\/pcbjunkie.net\/index.php\/wp-json\/wp\/v2\/media?parent=295"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}